1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Renesas Mobile SDHI 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Horms Solutions Ltd., Simon Horman 6*4882a593Smuzhiyun * Copyright (C) 2017-19 Renesas Electronics Corporation 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef RENESAS_SDHI_H 10*4882a593Smuzhiyun #define RENESAS_SDHI_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/platform_device.h> 13*4882a593Smuzhiyun #include "tmio_mmc.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct renesas_sdhi_scc { 16*4882a593Smuzhiyun unsigned long clk_rate; /* clock rate for SDR104 */ 17*4882a593Smuzhiyun u32 tap; /* sampling clock position for SDR104/HS400 (8 TAP) */ 18*4882a593Smuzhiyun u32 tap_hs400_4tap; /* sampling clock position for HS400 (4 TAP) */ 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct renesas_sdhi_of_data { 22*4882a593Smuzhiyun unsigned long tmio_flags; 23*4882a593Smuzhiyun u32 tmio_ocr_mask; 24*4882a593Smuzhiyun unsigned long capabilities; 25*4882a593Smuzhiyun unsigned long capabilities2; 26*4882a593Smuzhiyun enum dma_slave_buswidth dma_buswidth; 27*4882a593Smuzhiyun dma_addr_t dma_rx_offset; 28*4882a593Smuzhiyun unsigned int bus_shift; 29*4882a593Smuzhiyun int scc_offset; 30*4882a593Smuzhiyun struct renesas_sdhi_scc *taps; 31*4882a593Smuzhiyun int taps_num; 32*4882a593Smuzhiyun unsigned int max_blk_count; 33*4882a593Smuzhiyun unsigned short max_segs; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define SDHI_CALIB_TABLE_MAX 32 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct renesas_sdhi_quirks { 39*4882a593Smuzhiyun bool hs400_disabled; 40*4882a593Smuzhiyun bool hs400_4taps; 41*4882a593Smuzhiyun u32 hs400_bad_taps; 42*4882a593Smuzhiyun const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX]; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct tmio_mmc_dma { 46*4882a593Smuzhiyun enum dma_slave_buswidth dma_buswidth; 47*4882a593Smuzhiyun bool (*filter)(struct dma_chan *chan, void *arg); 48*4882a593Smuzhiyun void (*enable)(struct tmio_mmc_host *host, bool enable); 49*4882a593Smuzhiyun struct completion dma_dataend; 50*4882a593Smuzhiyun struct tasklet_struct dma_complete; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct renesas_sdhi { 54*4882a593Smuzhiyun struct clk *clk; 55*4882a593Smuzhiyun struct clk *clk_cd; 56*4882a593Smuzhiyun struct tmio_mmc_data mmc_data; 57*4882a593Smuzhiyun struct tmio_mmc_dma dma_priv; 58*4882a593Smuzhiyun const struct renesas_sdhi_quirks *quirks; 59*4882a593Smuzhiyun struct pinctrl *pinctrl; 60*4882a593Smuzhiyun struct pinctrl_state *pins_default, *pins_uhs; 61*4882a593Smuzhiyun void __iomem *scc_ctl; 62*4882a593Smuzhiyun u32 scc_tappos; 63*4882a593Smuzhiyun u32 scc_tappos_hs400; 64*4882a593Smuzhiyun const u8 *adjust_hs400_calib_table; 65*4882a593Smuzhiyun bool needs_adjust_hs400; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Tuning values: 1 for success, 0 for failure */ 68*4882a593Smuzhiyun DECLARE_BITMAP(taps, BITS_PER_LONG); 69*4882a593Smuzhiyun /* Sampling data comparison: 1 for match, 0 for mismatch */ 70*4882a593Smuzhiyun DECLARE_BITMAP(smpcmp, BITS_PER_LONG); 71*4882a593Smuzhiyun unsigned int tap_num; 72*4882a593Smuzhiyun unsigned int tap_set; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define host_to_priv(host) \ 76*4882a593Smuzhiyun container_of((host)->pdata, struct renesas_sdhi, mmc_data) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun int renesas_sdhi_probe(struct platform_device *pdev, 79*4882a593Smuzhiyun const struct tmio_mmc_dma_ops *dma_ops); 80*4882a593Smuzhiyun int renesas_sdhi_remove(struct platform_device *pdev); 81*4882a593Smuzhiyun #endif 82