Home
last modified time | relevance | path

Searched +full:cs +full:- +full:x (Results 1 – 25 of 1043) sorted by relevance

12345678910>>...42

/OK3568_Linux_fs/kernel/drivers/rkflash/
H A Dflash.c1 // SPDX-License-Identifier: GPL-2.0
48 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
52 nandc_flash_reset(cs); in flash_read_id_raw()
53 nandc_flash_cs(cs); in flash_read_id_raw()
54 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
55 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
58 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
60 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
61 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/u-boot/drivers/rkflash/
H A Dflash.c4 * SPDX-License-Identifier: GPL-2.0
47 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
51 nandc_flash_reset(cs); in flash_read_id_raw()
52 nandc_flash_cs(cs); in flash_read_id_raw()
53 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
54 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
57 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
58 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
60 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/
H A Dti-aemif.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
8 * Murali Karicheri <m-karicheri2@ti.com>
20 #include <linux/platform_data/ti-aemif.h>
32 #define TA(x) ((x) << TA_SHIFT) argument
33 #define RHOLD(x) ((x) << RHOLD_SHIFT) argument
34 #define RSTROBE(x) ((x) << RSTROBE_SHIFT) argument
35 #define RSETUP(x) ((x) << RSETUP_SHIFT) argument
36 #define WHOLD(x) ((x) << WHOLD_SHIFT) argument
37 #define WSTROBE(x) ((x) << WSTROBE_SHIFT) argument
[all …]
/OK3568_Linux_fs/external/xserver/composite/
H A Dcompwindow.c45 #include <dix-config.h>
58 ScreenPtr pScreen = pWin->drawable.pScreen; in compCheckWindow()
59 PixmapPtr pWinPixmap = (*pScreen->GetWindowPixmap) (pWin); in compCheckWindow()
61 pWin->parent ? (*pScreen->GetWindowPixmap) (pWin->parent) : 0; in compCheckWindow()
62 PixmapPtr pScreenPixmap = (*pScreen->GetScreenPixmap) (pScreen); in compCheckWindow()
64 if (!pWin->parent) { in compCheckWindow()
65 assert(pWin->redirectDraw == RedirectDrawNone); in compCheckWindow()
68 else if (pWin->redirectDraw != RedirectDrawNone) { in compCheckWindow()
75 assert(0 < pWinPixmap->refcnt && pWinPixmap->refcnt < 3); in compCheckWindow()
76 assert(0 < pScreenPixmap->refcnt && pScreenPixmap->refcnt < 3); in compCheckWindow()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
17 * regs has the to-be-set values for DDR controller registers
37 int csn = -1; in fsl_ddr_set_memctl_regs()
70 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
71 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
75 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
76 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
79 csn_bnds_backup = regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
80 csn_bnds_t = (unsigned int *) &regs->cs[i].bnds; in fsl_ddr_set_memctl_regs()
[all …]
/OK3568_Linux_fs/u-boot/drivers/spi/
H A Dfsl_espi.c4 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
43 #define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ argument
44 #define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ argument
46 #define ESPI_COM_CS(x) ((x) << 30) argument
47 #define ESPI_COM_TRANLEN(x) ((x) << 0) argument
53 #define ESPI_CSMODE_PM(x) ((x) << 24) argument
55 #define ESPI_CSMODE_LEN(x) ((x) << 16) argument
56 #define ESPI_CSMODE_CSBEF(x) ((x) << 12) argument
57 #define ESPI_CSMODE_CSAFT(x) ((x) << 8) argument
[all …]
H A Dmxc_spi.c4 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/imx-regs.h>
16 #include <asm/mach-imx/spi.h>
28 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) in board_spi_cs_gpio() argument
30 return -1; in board_spi_cs_gpio()
64 dm_gpio_set_value(&mxcs->ss, mxcs->ss_pol); in mxc_spi_cs_activate()
66 if (mxcs->gpio > 0) in mxc_spi_cs_activate()
67 gpio_set_value(mxcs->gpio, mxcs->ss_pol); in mxc_spi_cs_activate()
74 dm_gpio_set_value(&mxcs->ss, !(mxcs->ss_pol)); in mxc_spi_cs_deactivate()
76 if (mxcs->gpio > 0) in mxc_spi_cs_deactivate()
[all …]
H A Dbcm63xx_hsspi.c4 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
5 * Copyright (C) 2000-2010 Broadcom Corporation
6 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
8 * SPDX-License-Identifier: GPL-2.0+
41 /* SPI Ping-Pong Command registers */
50 /* SPI Ping-Pong Status registers */
56 #define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00) argument
63 #define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04) argument
72 #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08) argument
82 /* SPI Ping-Pong FIFO registers */
[all …]
H A Domap3_spi.c8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
17 * SPDX-License-Identifier: GPL-2.0+
44 /* per-register bitmasks */
105 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
106 /* channel1: 0x40 - 0x50, bus 0 & 1 */
107 /* channel2: 0x54 - 0x64, bus 0 & 1 */
108 /* channel3: 0x68 - 0x78, bus 0 */
116 unsigned int cs; member
125 writel(val, &priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
127 readl(&priv->regs->channel[priv->cs].chconf); in omap3_spi_write_chconf()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/slip/
H A Dslhc.c21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
43 * - Jan 1995 Bjorn Ekwall
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dselftest_workarounds.c2 * SPDX-License-Identifier: MIT
41 err = -EIO; in request_add_sync()
54 err = -ETIMEDOUT; in request_add_spin()
68 wa_init_start(&lists->gt_wa_list, "GT_REF", "global"); in reference_lists_init()
69 gt_init_workarounds(gt->i915, &lists->gt_wa_list); in reference_lists_init()
70 wa_init_finish(&lists->gt_wa_list); in reference_lists_init()
73 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
75 wa_init_start(wal, "REF", engine->name); in reference_lists_init()
80 &lists->engine[id].ctx_wa_list, in reference_lists_init()
92 intel_wa_list_free(&lists->engine[id].wa_list); in reference_lists_fini()
[all …]
H A Dselftest_lrc.c2 * SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
34 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
40 vma = i915_vma_instance(obj, &gt->ggtt->vm, NULL); in create_scratch()
82 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
86 return -ETIME; in wait_for_submit()
102 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
108 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
114 if (rq->fence.error != -EIO) { in wait_for_reset()
116 engine->name, in wait_for_reset()
[all …]
H A Dselftest_rps.c1 // SPDX-License-Identifier: MIT
22 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
33 return -1; in cmp_u64()
45 return -1; in cmp_u32()
64 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter() argument
68 u32 *base, *cs; in create_spin_counter() local
72 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
76 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
95 cs = base; in create_spin_counter()
97 *cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2); in create_spin_counter()
[all …]
H A Dintel_ring_submission.c2 * Copyright © 2008-2010 Intel Corporation
44 * set-context and then emitting the batch.
54 if (engine->class == RENDER_CLASS) { in set_hwstam()
55 if (INTEL_GEN(engine->i915) >= 6) in set_hwstam()
69 if (INTEL_GEN(engine->i915) >= 4) in set_hws_pga()
72 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
77 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
80 return sg_page(obj->mm.pages->sgl); in status_page()
97 if (IS_GEN(engine->i915, 7)) { in set_hwsp()
98 switch (engine->id) { in set_hwsp()
[all …]
/OK3568_Linux_fs/u-boot/examples/standalone/
H A Drkspi.c4 * SPDX-License-Identifier: GPL-2.0+
48 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0)); in rkspi_dump_regs()
49 debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1)); in rkspi_dump_regs()
50 debug("ssienr: \t\t0x%08x\n", readl(&regs->enr)); in rkspi_dump_regs()
51 debug("ser: \t\t0x%08x\n", readl(&regs->ser)); in rkspi_dump_regs()
52 debug("baudr: \t\t0x%08x\n", readl(&regs->baudr)); in rkspi_dump_regs()
53 debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr)); in rkspi_dump_regs()
54 debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr)); in rkspi_dump_regs()
55 debug("txflr: \t\t0x%08x\n", readl(&regs->txflr)); in rkspi_dump_regs()
56 debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr)); in rkspi_dump_regs()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_static.c4 * SPDX-License-Identifier: GPL-2.0
16 u32 g_zpri_data = 123; /* controller data - P drive strength */
17 u32 g_znri_data = 123; /* controller data - N drive strength */
18 u32 g_zpri_ctrl = 74; /* controller C/A - P drive strength */
19 u32 g_znri_ctrl = 74; /* controller C/A - N drive strength */
20 u32 g_zpodt_data = 45; /* controller data - P ODT */
21 u32 g_znodt_data = 45; /* controller data - N ODT */
22 u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
23 u32 g_znodt_ctrl = 45; /* controller data - N ODT */
46 /* CS Value (single only) Num_CS */
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-fsl-espi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4) argument
36 #define SPMODE_TXTHR(x) ((x) << 8) argument
37 #define SPMODE_RXTHR(x) ((x) << 0) argument
39 /* eSPI Controller CS mode register definitions */
44 #define CSMODE_PM(x) ((x) << 24) argument
46 #define CSMODE_LEN(x) ((x) << 16) argument
47 #define CSMODE_BEF(x) ((x) << 12) argument
48 #define CSMODE_AFT(x) ((x) << 8) argument
49 #define CSMODE_CG(x) ((x) << 3) argument
[all …]
H A Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
162 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
162 struct intel_gvt *gvt = engine->i915->gvt; in load_render_mocs()
163 struct intel_uncore *uncore = engine->uncore; in load_render_mocs()
164 u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt; in load_render_mocs()
165 u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list; in load_render_mocs()
174 if (!HAS_ENGINE(engine->gt, ring_id)) in load_render_mocs()
198 u32 *cs; in restore_context_mmio_for_inhibit() local
201 struct intel_gvt *gvt = vgpu->gvt; in restore_context_mmio_for_inhibit()
202 int ring_id = req->engine->id; in restore_context_mmio_for_inhibit()
203 int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id]; in restore_context_mmio_for_inhibit()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_drm_display_pattern.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Author: Sandy Huang <hjc@rock-chips.com>
28 (((-38 * (r) - 74 * (g) + 112 * (b) + 128) >> 8) + 128)
30 (((112 * (r) - 94 * (g) - 18 * (b) + 128) >> 8) + 128)
38 ((((r) >> (8 - (rgb)->red.length)) << (rgb)->red.offset) | \
39 (((g) >> (8 - (rgb)->green.length)) << (rgb)->green.offset) | \
40 (((b) >> (8 - (rgb)->blue.length)) << (rgb)->blue.offset) | \
41 (((a) >> (8 - (rgb)->alpha.length)) << (rgb)->alpha.offset))
46 /* YUV semi-planar */
105 MAKE_YUV_601(0, 33, 76), /* in-phase */ in fill_smpte_yuv_planar()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c1 // SPDX-License-Identifier: MIT
21 struct intel_context *ce = engine->kernel_context; in __igt_client_fill()
33 u32 sz = min_t(u64, ce->vm->total >> 4, prandom_u32_state(&prng)); in __igt_client_fill()
41 pr_debug("%s with phys_sz= %x, sz=%x, val=%x\n", __func__, in __igt_client_fill()
44 obj = huge_gem_object(engine->i915, phys_sz, sz); in __igt_client_fill()
61 * themselves may not yet be coherent with the GPU(swap-in). If in __igt_client_fill()
69 if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) in __igt_client_fill()
70 obj->cache_dirty = true; in __igt_client_fill()
72 err = i915_gem_schedule_fill_pages_blt(obj, ce, obj->mm.pages, in __igt_client_fill()
73 &obj->mm.page_sizes, in __igt_client_fill()
[all …]
/OK3568_Linux_fs/kernel/Documentation/scsi/
H A DNinjaSCSI.rst1 .. SPDX-License-Identifier: GPL-2.0
4 WorkBiT NinjaSCSI-3/32Bi driver for Linux
10 This is Workbit corp.'s(http://www.workbit.co.jp/) NinjaSCSI-3
17 :pcmcia-cs: 3.1.27
18 :gcc: gcc-2.95.4
19 :PC card: I-O data PCSC-F (NinjaSCSI-3),
20 I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi)
21 :SCSI device: I-O data CDPS-PX24 (CD-ROM drive),
22 Media Intelligent MMO-640GT (Optical disk drive)
27 (a) Check your PC card is true "NinjaSCSI-3" card.
[all …]
/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-sun5i.c6 * Maxime Ripard <maxime.ripard@free-electrons.com>
48 #define to_sun5i_timer(x) \ argument
49 container_of(x, struct sun5i_timer, clk_rate_cb)
56 #define to_sun5i_timer_clksrc(x) \ argument
57 container_of(x, struct sun5i_timer_clksrc, clksrc)
64 #define to_sun5i_timer_clkevt(x) \ argument
65 container_of(x, struct sun5i_timer_clkevt, clkevt)
75 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
77 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
83 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
[all …]

12345678910>>...42