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/OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
79 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
80 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
81 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
82 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
83 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
84 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
85 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
86 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c4 * SPDX-License-Identifier: GPL-2.0
47 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
60 * Args: freq - current sequence frequency
61 * dram_info - main struct
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
71 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
72 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
87 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
88 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
104 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c4 * SPDX-License-Identifier: GPL-2.0
45 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
49 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
57 * Args: dram_info - main struct
58 * freq - current sequence frequency
66 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
67 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
74 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
77 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
[all …]
H A Dddr3_spd.c4 * SPDX-License-Identifier: GPL-2.0
31 #define SPD_MODULE_TYPE_BYTE 3
41 #define SPD_ROW_NUM_OFF 3
53 #define SPD_MODULE_BANK_NUM_OFF 3
59 #define SPD_BUS_ECC_OFF 3
60 #define SPD_BUS_ECC_MASK (3 << SPD_BUS_ECC_OFF)
197 * Name: ddr3_get_dimm_num - Find number of dimms and their addresses
199 * Args: dimm_addr - array of dimm addresses
206 u8 data[3]; in ddr3_get_dimm_num()
212 dimm_cur_addr--) { in ddr3_get_dimm_num()
[all …]
H A Dddr3_dfs.c4 * SPDX-License-Identifier: GPL-2.0
73 /* Poll - Wait for Refresh operation completion */ in wait_refresh_op_complete()
83 * Args: target_freq - target frequency
85 * Returns: freq_par - the ratio parameter
96 /* Find the ratio between PLL frequency and ddr-clk */ in ddr3_get_freq_parameter()
109 * Args: freq - target frequency
111 * Returns: MV_OK - success, MV_FAIL - fail
118 u32 cs = 0; in ddr3_dfs_high_2_low() local
120 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
123 /* target frequency - 100MHz */ in ddr3_dfs_high_2_low()
[all …]
/OK3568_Linux_fs/u-boot/drivers/rkflash/
H A Dflash.c4 * SPDX-License-Identifier: GPL-2.0
47 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
51 nandc_flash_reset(cs); in flash_read_id_raw()
52 nandc_flash_cs(cs); in flash_read_id_raw()
53 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
54 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
57 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
58 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
60 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
H A Dm5407sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
19 #define CPU_INSTR_PER_JIFFY 3
41 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
[all …]
H A Dm5206sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
17 #define CPU_INSTR_PER_JIFFY 3
28 #define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
66 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
[all …]
/OK3568_Linux_fs/kernel/drivers/rkflash/
H A Dflash.c1 // SPDX-License-Identifier: GPL-2.0
48 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
52 nandc_flash_reset(cs); in flash_read_id_raw()
53 nandc_flash_cs(cs); in flash_read_id_raw()
54 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
55 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); in flash_read_id_raw()
58 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
59 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
60 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
61 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/kernel/sound/core/
H A Dpcm_iec958.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * snd_pcm_create_iec958_consumer_default - create default consumer format IEC958 channel status
14 * @cs: channel status buffer, at least four bytes
17 * Create the consumer format channel status data in @cs of maximum size
18 * @len. When relevant, the configuration-dependant bits will be set as
29 int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len) in snd_pcm_create_iec958_consumer_default() argument
32 return -EINVAL; in snd_pcm_create_iec958_consumer_default()
34 memset(cs, 0, len); in snd_pcm_create_iec958_consumer_default()
36 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; in snd_pcm_create_iec958_consumer_default()
37 cs[1] = IEC958_AES1_CON_GENERAL; in snd_pcm_create_iec958_consumer_default()
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
142 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
145 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23)
150 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
153 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16)
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/OK3568_Linux_fs/u-boot/drivers/spi/
H A Domap3_spi.c8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
17 * SPDX-License-Identifier: GPL-2.0+
44 /* per-register bitmasks */
45 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
54 #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
105 /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
106 /* channel1: 0x40 - 0x50, bus 0 & 1 */
107 /* channel2: 0x54 - 0x64, bus 0 & 1 */
108 /* channel3: 0x68 - 0x78, bus 0 */
116 unsigned int cs; member
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/OK3568_Linux_fs/buildroot/package/botan/
H A D0001-Revert-workaround-a-miscompilation-issue-in-clang-12.patch9 Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
11 ---
12 src/lib/hash/sha3/sha3.cpp | 46 ++++++-----------------
13 src/lib/hash/sha3/sha3_bmi2/sha3_bmi2.cpp | 46 ++++++-----------------
14 2 files changed, 22 insertions(+), 70 deletions(-)
16 diff --git a/src/lib/hash/sha3/sha3.cpp b/src/lib/hash/sha3/sha3.cpp
18 --- a/src/lib/hash/sha3/sha3.cpp
20 @@ -11,47 +11,23 @@
24 -#include <tuple>
25 -
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/OK3568_Linux_fs/kernel/drivers/s390/char/
H A Draw3270.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define TUBICMD _IO('3', 3) /* set ccw command for fs reads. */
16 #define TUBOCMD _IO('3', 4) /* set ccw command for fs writes. */
17 #define TUBGETI _IO('3', 7) /* get ccw command for fs reads. */
18 #define TUBGETO _IO('3', 8) /* get ccw command for fs writes. */
19 #define TUBSETMOD _IO('3',12) /* FIXME: what does it do ?*/
20 #define TUBGETMOD _IO('3',13) /* FIXME: what does it do ?*/
44 #define TF_INMDT 0xc1 /* Visible, Set-MDT */
55 /* Extended-Highlighting Bytes */
123 return list_empty(&rq->list); in raw3270_request_final()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c2 * Copyright 2008-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
17 * regs has the to-be-set values for DDR controller registers
37 int csn = -1; in fsl_ddr_set_memctl_regs()
57 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) in fsl_ddr_set_memctl_regs()
58 case 3: in fsl_ddr_set_memctl_regs()
70 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
71 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
75 cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; in fsl_ddr_set_memctl_regs()
76 cs_ea = regs->cs[i].bnds & 0xfff; in fsl_ddr_set_memctl_regs()
[all …]
/OK3568_Linux_fs/u-boot/board/atmel/at91sam9261ek/
H A Dat91sam9261ek.c2 * (C) Copyright 2007-2008
6 * SPDX-License-Identifier: GPL-2.0+
25 #include <asm/mach-types.h>
29 /* ------------------------------------------------------------------------- */
42 csa = readl(&matrix->ebicsa); in at91sam9261ek_nand_hw_init()
45 writel(csa, &matrix->ebicsa); in at91sam9261ek_nand_hw_init()
51 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) | in at91sam9261ek_nand_hw_init()
53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7), in at91sam9261ek_nand_hw_init()
54 &smc->cs[3].pulse); in at91sam9261ek_nand_hw_init()
[all …]
/OK3568_Linux_fs/u-boot/cmd/
H A Dmmc_spi.c5 * Licensed under the GPL-2 or later.
23 * rising edge ... meaning SPI modes 0 or 3. So either SPI mode
26 * specify mode 3 (if hardware is not compatible to mode 0).
35 uint cs = CONFIG_MMC_SPI_CS; in do_mmc_spi() local
44 cs = simple_strtoul(argv[1], &endp, 0); in do_mmc_spi()
50 bus = cs; in do_mmc_spi()
51 cs = simple_strtoul(endp + 1, &endp, 0); in do_mmc_spi()
55 if (argc >= 3) { in do_mmc_spi()
61 mode = simple_strtoul(argv[3], &endp, 16); in do_mmc_spi()
62 if (*argv[3] == 0 || *endp != 0) in do_mmc_spi()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c4 * SPDX-License-Identifier: GPL-2.0
16 #include "../../../../arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h"
112 * sys_env_device_rev_get - Get Marvell controller device revision number
162 * DESCRIPTION: Get bit mask of enabled CS
169 * Bit mask of enabled CS, 1 if only CS0 enabled,
170 * 3 if both CS0 and CS1 enabled
187 /* Return XBAR windows 4-7 or 16-19 init configuration */ in ddr3_restore_and_set_final_windows()
191 printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n", in ddr3_restore_and_set_final_windows()
198 u32 reg, cs; in ddr3_restore_and_set_final_windows() local
200 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dselftest_engine_cs.c2 * SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(&gt->rps.num_waiters); in perf_begin()
30 schedule_work(&gt->rps.work); in perf_begin()
31 flush_work(&gt->rps.work); in perf_begin()
36 atomic_dec(&gt->rps.num_waiters); in perf_end()
39 return igt_flush_test(gt->i915); in perf_end()
45 u32 *cs; in write_timestamp() local
47 cs = intel_ring_begin(rq, 4); in write_timestamp()
48 if (IS_ERR(cs)) in write_timestamp()
[all …]
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
36 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
[all …]
/OK3568_Linux_fs/kernel/Documentation/scsi/
H A DNinjaSCSI.rst1 .. SPDX-License-Identifier: GPL-2.0
4 WorkBiT NinjaSCSI-3/32Bi driver for Linux
10 This is Workbit corp.'s(http://www.workbit.co.jp/) NinjaSCSI-3
17 :pcmcia-cs: 3.1.27
18 :gcc: gcc-2.95.4
19 :PC card: I-O data PCSC-F (NinjaSCSI-3),
20 I-O data CBSC-II in 16 bit mode (NinjaSCSI-32Bi)
21 :SCSI device: I-O data CDPS-PX24 (CD-ROM drive),
22 Media Intelligent MMO-640GT (Optical disk drive)
24 3. Install
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c2 * SPDX-License-Identifier: MIT
17 #define TEST_OA_CONFIG_UUID "12345678-1234-1234-1234-1234567890ab"
26 return -ENOMEM; in alloc_empty_config()
28 oa_config->perf = perf; in alloc_empty_config()
29 kref_init(&oa_config->ref); in alloc_empty_config()
31 strlcpy(oa_config->uuid, TEST_OA_CONFIG_UUID, sizeof(oa_config->uuid)); in alloc_empty_config()
33 mutex_lock(&perf->metrics_lock); in alloc_empty_config()
35 oa_config->id = idr_alloc(&perf->metrics_idr, oa_config, 2, 0, GFP_KERNEL); in alloc_empty_config()
36 if (oa_config->id < 0) { in alloc_empty_config()
37 mutex_unlock(&perf->metrics_lock); in alloc_empty_config()
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
[all …]
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
65 * We still return -ERANGE in case the caller cares. in atmel_smc_cs_encode_ncycles()
[all …]

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