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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
24 * 0.
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
H A Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
10 #define GT3_INLINE_DATA_DELAYS 0x1E00
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
[all …]
H A Dgen2_engine_cs.c1 // SPDX-License-Identifier: MIT
17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
28 while (num_store_dw--) { in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c4 * SPDX-License-Identifier: GPL-2.0
44 #define WL_SUP_EXPECTED_DATA 0x21
45 #define WL_SUP_READ_DRAM_ENTRY 0x8
47 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
60 * Args: freq - current sequence frequency
61 * dram_info - main struct
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
69 int dpde_flag = 0; in ddr3_write_leveling_hw()
71 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
72 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c4 * SPDX-License-Identifier: GPL-2.0
45 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
49 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
57 * Args: dram_info - main struct
58 * freq - current sequence frequency
66 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
67 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
74 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
75 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
77 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
[all …]
/OK3568_Linux_fs/external/security/rk_tee_user/v2/host/xtest/
H A Dregression_5000.c1 // SPDX-License-Identifier: GPL-2.0
17 #define OFFSET0 0
19 #define PARAM_0 0
35 (op)->params[(param_num)].memref.size); \
38 (op)->params[(param_num)].memref.parent); \
40 (shrm)->buffer, \
41 (op)->params[(param_num)].memref.size); \
43 } while (0)
53 (op)->params[(param_num)].tmpref.size); \
56 (op)->params[(param_num)].tmpref.buffer); \
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/
H A Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
52 for (i = 0; i < ARRAY_SIZE(myrs_devstate_name_list); i++) { in myrs_devstate_name()
83 for (i = 0; i < ARRAY_SIZE(myrs_raid_level_name_list); i++) { in myrs_raid_level_name()
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
97 memset(mbox, 0, sizeof(union myrs_cmd_mbox)); in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
[all …]
/OK3568_Linux_fs/kernel/drivers/rkflash/
H A Dflash.c1 // SPDX-License-Identifier: GPL-2.0
16 #define FLASH_STRESS_TEST_EN 0
28 {0x98, 0xF1, 0, 0, 0, 0},
36 0x100,
42 0,
45 {0}
48 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
52 nandc_flash_reset(cs); in flash_read_id_raw()
53 nandc_flash_cs(cs); in flash_read_id_raw()
54 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
10 #define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
11 #define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
12 #define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45
13 #define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912
14 #define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40
15 #define CONFIG_SYS_DDR_MODE_2_1200 0x00100000
16 #define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100
17 #define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000
[all …]
/OK3568_Linux_fs/u-boot/drivers/rkflash/
H A Dflash.c4 * SPDX-License-Identifier: GPL-2.0
15 #define FLASH_STRESS_TEST_EN 0
27 {0x98, 0xF1, 0, 0, 0, 0},
35 0x100,
41 0,
44 {0}
47 static void flash_read_id_raw(u8 cs, u8 *buf) in flash_read_id_raw() argument
51 nandc_flash_reset(cs); in flash_read_id_raw()
52 nandc_flash_cs(cs); in flash_read_id_raw()
53 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); in flash_read_id_raw()
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
16 #define FMC2_BCR1 0x0
17 #define FMC2_BTR1 0x4
18 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1)
19 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1)
20 #define FMC2_PCSCNTR 0x20
21 #define FMC2_BWTR1 0x104
22 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1)
29 #define FMC2_BCR_MBKEN BIT(0)
46 #define FMC2_BXTR_ADDSET GENMASK(3, 0)
[all …]
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
39 #define GPMC_REVISION 0x00
40 #define GPMC_SYSCONFIG 0x10
41 #define GPMC_SYSSTATUS 0x14
42 #define GPMC_IRQSTATUS 0x18
[all …]
/OK3568_Linux_fs/kernel/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include "tick-internal.h"
22 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
57 sftacc--; in clocks_calc_mult_shift()
64 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
68 if ((tmp >> sftacc) == 0) in clocks_calc_mult_shift()
76 /*[Clocksource internal variables]---------
86 * Name of the user-specified clocksource.
119 static void __clocksource_change_rating(struct clocksource *cs, int rating);
152 static void __clocksource_unstable(struct clocksource *cs) in __clocksource_unstable() argument
[all …]
/OK3568_Linux_fs/external/xserver/composite/
H A Dcompinit.c45 #include <dix-config.h>
58 CompScreenPtr cs = GetCompScreen(pScreen); in compCloseScreen() local
61 free(cs->alternateVisuals); in compCloseScreen()
63 pScreen->CloseScreen = cs->CloseScreen; in compCloseScreen()
64 pScreen->InstallColormap = cs->InstallColormap; in compCloseScreen()
65 pScreen->ChangeWindowAttributes = cs->ChangeWindowAttributes; in compCloseScreen()
66 pScreen->ReparentWindow = cs->ReparentWindow; in compCloseScreen()
67 pScreen->ConfigNotify = cs->ConfigNotify; in compCloseScreen()
68 pScreen->MoveWindow = cs->MoveWindow; in compCloseScreen()
69 pScreen->ResizeWindow = cs->ResizeWindow; in compCloseScreen()
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/common/
H A Dcommand_submission.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
25 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
27 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
34 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset_error()
36 dev_crit(hdev->dev, in hl_sob_reset_error()
38 hw_sob->q_idx, hw_sob->sob_id); in hl_sob_reset_error()
47 struct hl_device *hdev = hl_cs_cmpl->hdev; in hl_fence_release()
49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
52 if (fence->error == -EBUSY) in hl_fence_release()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
H A Dst,stm32-fmc2-ebi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
37 "#address-cells":
[all …]
/OK3568_Linux_fs/kernel/drivers/mfd/
H A Datmel-smc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
18 * Set all fields to 0 so that one can start defining a new config.
22 memset(conf, 0, sizeof(*conf)); in atmel_smc_cs_conf_init()
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
41 * the encodedval is contains the maximum val. Otherwise, 0 is returned.
[all …]
/OK3568_Linux_fs/kernel/fs/fuse/
H A Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
30 #define FUSE_INT_REQ_BIT (1ULL << 0)
38 * Lockless access is OK, because file->private data is set in fuse_get_dev()
41 return READ_ONCE(file->private_data); in fuse_get_dev()
46 INIT_LIST_HEAD(&req->list); in fuse_request_init()
47 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
48 init_waitqueue_head(&req->waitq); in fuse_request_init()
49 refcount_set(&req->count, 1); in fuse_request_init()
50 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
51 req->fm = fm; in fuse_request_init()
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
[all …]
/OK3568_Linux_fs/kernel/kernel/cgroup/
H A Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
60 #include <linux/backing-dev.h>
93 * The user-configured masks can only be changed by writing to
107 * The user-configured masks are always the same with effective masks.
110 /* user-configured CPUs and Memory Nodes allow to tasks */
120 * CPUs allocated to child sub-partitions (default hierarchy only)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c8 * Copyright (C) 2004-2010
9 * Texas Instruments Incorporated - http://www.ti.com/
12 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
22 * SPDX-License-Identifier: GPL-2.0+
36 * is_mem_sdr -
37 * - Return 1 if mem type in use is SDR
41 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
43 return 0; in is_mem_sdr()
47 * make_cs1_contiguous -
48 * - When we have CS1 populated we want to have it mapped after cs0 to allow
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/OK3568_Linux_fs/u-boot/drivers/spi/
H A Domap3_spi.c8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
17 * SPDX-License-Identifier: GPL-2.0+
29 #define OMAP3_MCSPI1_BASE 0x48030100
30 #define OMAP3_MCSPI2_BASE 0x481A0100
32 #define OMAP3_MCSPI1_BASE 0x48098000
33 #define OMAP3_MCSPI2_BASE 0x4809A000
34 #define OMAP3_MCSPI3_BASE 0x480B8000
35 #define OMAP3_MCSPI4_BASE 0x480BA000
38 #define OMAP4_MCSPI_REG_OFFSET 0x100
44 /* per-register bitmasks */
[all …]
H A Dbcm63xx_hsspi.c4 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
5 * Copyright (C) 2000-2010 Broadcom Corporation
6 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
8 * SPDX-License-Identifier: GPL-2.0+
21 #define HSSPI_PP 0
26 #define SPI_CTL_REG 0x000
27 #define SPI_CTL_CS_POL_SHIFT 0
28 #define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
35 #define SPI_IR_STAT_REG 0x008
36 #define SPI_IR_ST_MASK_REG 0x00c
[all …]

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