Lines Matching +full:cs +full:- +full:0
4 * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
5 * Copyright (C) 2000-2010 Broadcom Corporation
6 * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
8 * SPDX-License-Identifier: GPL-2.0+
21 #define HSSPI_PP 0
26 #define SPI_CTL_REG 0x000
27 #define SPI_CTL_CS_POL_SHIFT 0
28 #define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
35 #define SPI_IR_STAT_REG 0x008
36 #define SPI_IR_ST_MASK_REG 0x00c
37 #define SPI_IR_MASK_REG 0x010
39 #define SPI_IR_CLEAR_ALL 0xff001f1f
41 /* SPI Ping-Pong Command registers */
42 #define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
43 #define SPI_CMD_OP_SHIFT 0
44 #define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
46 #define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
48 #define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
50 /* SPI Ping-Pong Status registers */
51 #define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
56 #define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
57 #define SPI_PFL_CLK_FREQ_SHIFT 0
58 #define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
63 #define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
72 #define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
73 #define SPI_PFL_MODE_FILL_SHIFT 0
74 #define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
82 /* SPI Ping-Pong FIFO registers */
83 #define HSSPI_FIFO_SIZE 0x200
84 #define HSSPI_FIFO_BASE (0x200 + \
87 /* SPI Ping-Pong FIFO OP register */
88 #define HSSPI_FIFO_OP_SIZE 0x2
89 #define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
90 #define HSSPI_FIFO_OP_BYTES_SHIFT 0
91 #define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
107 static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs, in bcm63xx_hsspi_cs_info() argument
112 if (cs >= priv->num_cs) { in bcm63xx_hsspi_cs_info()
113 printf("no cs %u\n", cs); in bcm63xx_hsspi_cs_info()
114 return -ENODEV; in bcm63xx_hsspi_cs_info()
117 return 0; in bcm63xx_hsspi_cs_info()
126 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); in bcm63xx_hsspi_set_mode()
128 clrbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK); in bcm63xx_hsspi_set_mode()
130 return 0; in bcm63xx_hsspi_set_mode()
137 priv->speed = speed; in bcm63xx_hsspi_set_speed()
139 return 0; in bcm63xx_hsspi_set_speed()
148 set = DIV_ROUND_UP(priv->clk_rate, priv->speed); in bcm63xx_hsspi_activate_cs()
152 writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); in bcm63xx_hsspi_activate_cs()
155 set = 0; in bcm63xx_hsspi_activate_cs()
161 if (plat->mode & SPI_CPHA) in bcm63xx_hsspi_activate_cs()
167 if (priv->speed > SPI_MAX_SYNC_CLOCK) in bcm63xx_hsspi_activate_cs()
170 clrsetbits_be32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set); in bcm63xx_hsspi_activate_cs()
173 set = 0; in bcm63xx_hsspi_activate_cs()
174 clr = 0; in bcm63xx_hsspi_activate_cs()
176 /* invert cs polarity */ in bcm63xx_hsspi_activate_cs()
177 if (priv->cs_pols & BIT(plat->cs)) in bcm63xx_hsspi_activate_cs()
178 clr |= BIT(plat->cs); in bcm63xx_hsspi_activate_cs()
180 set |= BIT(plat->cs); in bcm63xx_hsspi_activate_cs()
182 /* invert dummy cs polarity */ in bcm63xx_hsspi_activate_cs()
183 if (priv->cs_pols & BIT(!plat->cs)) in bcm63xx_hsspi_activate_cs()
184 clr |= BIT(!plat->cs); in bcm63xx_hsspi_activate_cs()
186 set |= BIT(!plat->cs); in bcm63xx_hsspi_activate_cs()
188 clrsetbits_be32(priv->regs + SPI_CTL_REG, clr, set); in bcm63xx_hsspi_activate_cs()
193 /* restore cs polarities */ in bcm63xx_hsspi_deactivate_cs()
194 clrsetbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK, in bcm63xx_hsspi_deactivate_cs()
195 priv->cs_pols); in bcm63xx_hsspi_deactivate_cs()
199 * BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
203 * SPI-connected flashes since reading requires prepending a write transfer of
204 * 5 bytes. On the other hand it also provides a way to invert each CS
209 * polarity of both the desired CS and another dummy CS when the bus is
210 * claimed. This way, the dummy CS is restored to its inactive value when
211 * transfers are issued and the desired CS is preserved in its active value
213 * allows keeping CS active between trasnfers even if the HW doesn't give
219 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); in bcm63xx_hsspi_xfer()
223 uint16_t opcode = 0; in bcm63xx_hsspi_xfer()
240 step_size -= HSSPI_FIFO_OP_SIZE; in bcm63xx_hsspi_xfer()
243 if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) || in bcm63xx_hsspi_xfer()
244 (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL)) in bcm63xx_hsspi_xfer()
251 if (plat->mode & SPI_3WIRE) in bcm63xx_hsspi_xfer()
253 writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); in bcm63xx_hsspi_xfer()
256 while (data_bytes > 0) { in bcm63xx_hsspi_xfer()
262 memcpy_toio(priv->regs + HSSPI_FIFO_BASE + in bcm63xx_hsspi_xfer()
269 priv->regs + HSSPI_FIFO_OP_REG); in bcm63xx_hsspi_xfer()
273 val |= (plat->cs << SPI_CMD_PFL_SHIFT) & in bcm63xx_hsspi_xfer()
275 val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) & in bcm63xx_hsspi_xfer()
277 writel_be(val, priv->regs + SPI_CMD_REG); in bcm63xx_hsspi_xfer()
280 ret = wait_for_bit_be32(priv->regs + SPI_STAT_REG, in bcm63xx_hsspi_xfer()
290 memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE, in bcm63xx_hsspi_xfer()
295 data_bytes -= curr_step; in bcm63xx_hsspi_xfer()
301 return 0; in bcm63xx_hsspi_xfer()
312 { .compatible = "brcm,bcm6328-hsspi", },
318 struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent); in bcm63xx_hsspi_child_pre_probe()
321 /* check cs */ in bcm63xx_hsspi_child_pre_probe()
322 if (plat->cs >= priv->num_cs) { in bcm63xx_hsspi_child_pre_probe()
323 printf("no cs %u\n", plat->cs); in bcm63xx_hsspi_child_pre_probe()
324 return -ENODEV; in bcm63xx_hsspi_child_pre_probe()
327 /* cs polarity */ in bcm63xx_hsspi_child_pre_probe()
328 if (plat->mode & SPI_CS_HIGH) in bcm63xx_hsspi_child_pre_probe()
329 priv->cs_pols |= BIT(plat->cs); in bcm63xx_hsspi_child_pre_probe()
331 priv->cs_pols &= ~BIT(plat->cs); in bcm63xx_hsspi_child_pre_probe()
333 return 0; in bcm63xx_hsspi_child_pre_probe()
345 addr = devfdt_get_addr_size_index(dev, 0, &size); in bcm63xx_hsspi_probe()
347 return -EINVAL; in bcm63xx_hsspi_probe()
349 priv->regs = ioremap(addr, size); in bcm63xx_hsspi_probe()
350 priv->num_cs = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), in bcm63xx_hsspi_probe()
351 "num-cs", 8); in bcm63xx_hsspi_probe()
355 if (ret < 0) in bcm63xx_hsspi_probe()
359 if (ret < 0) in bcm63xx_hsspi_probe()
363 if (ret < 0) in bcm63xx_hsspi_probe()
368 if (ret < 0) in bcm63xx_hsspi_probe()
371 priv->clk_rate = clk_get_rate(&clk); in bcm63xx_hsspi_probe()
374 if (ret < 0) in bcm63xx_hsspi_probe()
378 ret = reset_get_by_index(dev, 0, &rst_ctl); in bcm63xx_hsspi_probe()
379 if (ret < 0) in bcm63xx_hsspi_probe()
383 if (ret < 0) in bcm63xx_hsspi_probe()
387 if (ret < 0) in bcm63xx_hsspi_probe()
391 writel_be(0, priv->regs + SPI_IR_MASK_REG); in bcm63xx_hsspi_probe()
394 writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); in bcm63xx_hsspi_probe()
397 setbits_be32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK); in bcm63xx_hsspi_probe()
399 /* read default cs polarities */ in bcm63xx_hsspi_probe()
400 priv->cs_pols = readl_be(priv->regs + SPI_CTL_REG) & in bcm63xx_hsspi_probe()
403 return 0; in bcm63xx_hsspi_probe()