8  * Copyright (C) 2004-2010
9  * Texas Instruments Incorporated - http://www.ti.com/
12  * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
22  * SPDX-License-Identifier:	GPL-2.0+
36  * is_mem_sdr -
37  *  - Return 1 if mem type in use is SDR
41 	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)  in is_mem_sdr()
43 	return 0;  in is_mem_sdr()
47  * make_cs1_contiguous -
48  * - When we have CS1 populated we want to have it mapped after cs0 to allow
59 	a_add_low = (size & 0x3C) >> 2;	/* set up high field */  in make_cs1_contiguous()
60 	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);  in make_cs1_contiguous()
66  * get_sdr_cs_size -
67  *  - Get size of chip select 0/1
69 u32 get_sdr_cs_size(u32 cs)  in get_sdr_cs_size()  argument
74 	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;  in get_sdr_cs_size()
75 	size &= 0x3FF;		/* remove unwanted bits */  in get_sdr_cs_size()
81  * get_sdr_cs_offset -
82  *  - Get offset of cs from cs0 start
84 u32 get_sdr_cs_offset(u32 cs)  in get_sdr_cs_offset()  argument
88 	if (!cs)  in get_sdr_cs_offset()
89 		return 0;  in get_sdr_cs_offset()
91 	offset = readl(&sdrc_base->cs_cfg);  in get_sdr_cs_offset()
92 	offset = (offset & 15) << 27 | (offset & 0x300) << 17;  in get_sdr_cs_offset()
98  * write_sdrc_timings -
99  *  - Takes CS and associated timings and initalize SDRAM
100  *  - Test CS to make sure it's OK for use
102 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,  in write_sdrc_timings()  argument
106 	writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);  in write_sdrc_timings()
107 	writel(timings->ctrla, &sdrc_actim_base->ctrla);  in write_sdrc_timings()
108 	writel(timings->ctrlb, &sdrc_actim_base->ctrlb);  in write_sdrc_timings()
109 	writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);  in write_sdrc_timings()
110 	writel(CMD_NOP, &sdrc_base->cs[cs].manual);  in write_sdrc_timings()
111 	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);  in write_sdrc_timings()
112 	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);  in write_sdrc_timings()
113 	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);  in write_sdrc_timings()
114 	writel(timings->mr, &sdrc_base->cs[cs].mr);  in write_sdrc_timings()
120 	if (!mem_ok(cs))  in write_sdrc_timings()
121 		writel(0, &sdrc_base->cs[cs].mcfg);  in write_sdrc_timings()
125  * do_sdrc_init -
126  *  - Code called once in C-Stack only context for CS0 and with early being
130 void do_sdrc_init(u32 cs, u32 early)  in do_sdrc_init()  argument
151 	/* set/modify board-specific timings */  in do_sdrc_init()
156 		writel(SOFTRESET, &sdrc_base->sysconfig);  in do_sdrc_init()
157 		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,  in do_sdrc_init()
159 		writel(0, &sdrc_base->sysconfig);  in do_sdrc_init()
162 		writel(timings.sharing, &sdrc_base->sharing);  in do_sdrc_init()
166 				&sdrc_base->power);  in do_sdrc_init()
168 		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);  in do_sdrc_init()
169 		sdelay(0x20000);  in do_sdrc_init()
181 	 * both CS0 and CS1 (such as some older versions of x-loader)  in do_sdrc_init()
184 	if (cs == CS1) {  in do_sdrc_init()
185 		timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),  in do_sdrc_init()
186 		timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);  in do_sdrc_init()
187 		timings.ctrla = readl(&sdrc_actim_base0->ctrla);  in do_sdrc_init()
188 		timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);  in do_sdrc_init()
189 		timings.mr = readl(&sdrc_base->cs[CS0].mr);  in do_sdrc_init()
190 		write_sdrc_timings(cs, sdrc_actim_base1, &timings);  in do_sdrc_init()
195  * dram_init -
196  *  - Sets uboots idea of sdram size
200 	unsigned int size0 = 0, size1 = 0;  in dram_init()
214 	gd->ram_size = size0 + size1;  in dram_init()
216 	return 0;  in dram_init()
221 	unsigned int size0 = 0, size1 = 0;  in dram_init_banksize()
226 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;  in dram_init_banksize()
227 	gd->bd->bi_dram[0].size = size0;  in dram_init_banksize()
228 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);  in dram_init_banksize()
229 	gd->bd->bi_dram[1].size = size1;  in dram_init_banksize()
231 	return 0;  in dram_init_banksize()
235  * mem_init -
236  *  - Init the sdrc chip,
237  *  - Selects CS0 and CS1,