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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-sched-energy.dtsi29 210 129 /* 408MHz */
30 308 184 /* 600MHz */
31 419 246 /* 816MHz */
32 518 335 /* 1008MHz */
33 617 428 /* 1200MHz */
34 728 573 /* 1416MHz */
35 827 724 /* 1608MHz */
36 925 900 /* 1800MHz */
37 1024 1108 /* 1992MHz */
67 210 129 /* 408MHz */
[all …]
H A Drk3588-vehicle-serdes-display-v21.dtsi19 64 65 66 67 68 69 70 71
58 64 65 66 67 68 69 70 71
97 64 65 66 67 68 69 70 71
136 64 65 66 67 68 69 70 71
175 64 65 66 67 68 69 70 71
654 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
795 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
797 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
870 //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M
1010 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz
[all …]
H A Drk3562j.dtsi23 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
62 * Max GPU frequency is 900MHz for the overdrive mode,
88 * Max NPU frequency is 900MHz for the overdrive mode,
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/
H A Drtw_general_def.h441 * RU484 : 65 66
446 /* 20MHz - 1 */
456 /* 20MHz - 2 */
468 /* 20MHz - 3 */
478 /* 20MHz - 4 */
488 /* 20MHz - 1 */
493 /* 20MHz - 2 */
498 /* 20MHz - 3 */
503 /* 20MHz - 4 */
508 /* 20MHz - 1 */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/
H A Drtw_general_def.h441 * RU484 : 65 66
446 /* 20MHz - 1 */
456 /* 20MHz - 2 */
468 /* 20MHz - 3 */
478 /* 20MHz - 4 */
488 /* 20MHz - 1 */
493 /* 20MHz - 2 */
498 /* 20MHz - 3 */
503 /* 20MHz - 4 */
508 /* 20MHz - 1 */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/wcn36xx/
H A Dtxrx.c65 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
85 { 65, 0, RX_ENC_HT, RX_ENC_FLAG_HT_GF, RATE_INFO_BW_20 },
128 /* 11ac 20 MHz 800ns GI MCS 0-8 */
129 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
150 /* 11ac 20 MHz 400ns SGI MCS 6-8 */
160 /* 11ac 40 MHz 800ns GI MCS 0-9 */
181 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
189 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
196 /* 11ac 80 MHz 800ns GI MCS 0-7 */
209 /* 11ac 80 MHz 800 ns GI MCS 8-9 */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx7/
H A Dclock.h51 PLL_USB, /* USB PLL, fixed at 480MHZ */
89 PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
115 DRAM_ALT_CLK_ROOT = 65,
225 CCGR_SEMA2 = 65,
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dstm32mp157a-dk1-u-boot.dtsi140 /* VCO = 1300.0 MHz => P = 650 (CPU) */
147 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
149 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
154 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
161 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
/OK3568_Linux_fs/yocto/meta-openembedded/meta-oe/recipes-support/fbset/fbset-modes/omap3-pandora/
H A Dfb.modes1 mode "800x480-65"
2 # D: 36.001 MHz, H: 34.124 kHz, V: 64.998 Hz
/OK3568_Linux_fs/rkbin/tools/
H A Dddrbin_tool_user_guide.txt159 ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz.
160 lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz.
161 ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz.
162 lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz.
163 ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz.
164 lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz.
165 lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz.
166 lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz.
171 | platform | support frequencies(MHZ) |
202 | RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] |
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rv1126.h12 #define MHz 1000000 macro
14 #define OSC_HZ (24 * MHz)
17 #define APLL_HZ (1008 * MHz)
19 #define APLL_HZ (816 * MHz)
21 #define GPLL_HZ (1188 * MHz)
22 #define CPLL_HZ (500 * MHz)
23 #define HPLL_HZ (1400 * MHz)
24 #define PCLK_PDPMU_HZ (100 * MHz)
26 #define ACLK_PDBUS_HZ (396 * MHz)
28 #define ACLK_PDBUS_HZ (500 * MHz)
[all …]
/OK3568_Linux_fs/kernel/arch/x86/kernel/cpu/
H A Dtransmeta.c27 char cpu_info[65]; in init_transmeta()
39 pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", in init_transmeta()
50 pr_info("CPU: Processor revision %08X, %u MHz\n", in init_transmeta()
/OK3568_Linux_fs/kernel/Documentation/hwmon/
H A Dadm1021.rst119 are possible between -65 and +127 degrees, with a resolution of one degree.
137 era (with 400 MHz FSB) had chips with only one temperature sensor.
150 didn't have these sensors. Next generations of Xeon processors (533 MHz
/OK3568_Linux_fs/kernel/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
100 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
101 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
102 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
128 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/spear/
H A Dspear1340_clock.c167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
181 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dmpc5125twr.dts39 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
40 bus-frequency = <198000000>; // 198 MHz csb bus
41 clock-frequency = <396000000>; // 396 MHz ppc core
72 bus-frequency = <66000000>; // 66 MHz ips bus
289 interrupts = <65 0x8>;
/OK3568_Linux_fs/yocto/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dhu-Szentes-Battonya23 # T 538000000 8MHz 3/4 NONE QAM64 8k 1/4 NONE
25 # C.multiplex UHF-65:
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dmxl5xx_defs.h103 MXL_XCPU_PID_FLT_CFG_CMD = 65,
400 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
405 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
406 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
407 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
408 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
437 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
[all …]
/OK3568_Linux_fs/kernel/drivers/media/tuners/
H A Dfc0012.c217 /* fix for frequency less than 45 MHz */ in fc0012_set_params()
348 -63, -65, -54, -60, in fc0012_get_rf_strength()
351 65, 63, 61, 58, in fc0012_get_rf_strength()
411 .frequency_min_hz = 37 * MHz, /* estimate */
412 .frequency_max_hz = 862 * MHz, /* estimate */
/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
68 .m2 = {.min = 65, .max = 130},
92 .m2 = {.min = 65, .max = 130},
625 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
628 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
635 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
636 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose in cdv_intel_crtc_mode_set()
637 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. in cdv_intel_crtc_mode_set()
647 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/versatile/
H A Dclk-icst.c107 * 33 or 25 MHz respectively. in vco_get()
262 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
267 /* Slam to closest 0.25 MHz */ in icst_round_rate()
273 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
274 * select 25 MHz in icst_round_rate()
415 .rd_max = 65,
438 /* Minimum 12 MHz, VDW = 4 */
441 * Maximum 160 MHz, VDW = 152 for all core modules, but
443 * go to 200 MHz (max VDW = 192).
456 /* Minimum 3 MHz, VDW = 4 */
[all …]
/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628_combrxphy.c368 * 5'd18:rx3p clock = 297MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
369 * 5'd17:rx3p clock = 162MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
370 * 5'd16:rx3p clock = 148.5MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
371 * 5'd15:rx3p clock = 135MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
372 * 5'd14:rx3p clock = 119MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
373 * 5'd13:rx3p clock = 108MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
374 * 5'd12:rx3p clock = 101MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
375 * 5'd11:rx3p clock = 92.8125MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
376 * 5'd10:rx3p clock = 88.75MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
377 * 5'd9:rx3p clock = 85.5MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_combrxphy.c359 * 5'd18:rx3p clock = 297MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
360 * 5'd17:rx3p clock = 162MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
361 * 5'd16:rx3p clock = 148.5MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
362 * 5'd15:rx3p clock = 135MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
363 * 5'd14:rx3p clock = 119MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
364 * 5'd13:rx3p clock = 108MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
365 * 5'd12:rx3p clock = 101MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
366 * 5'd11:rx3p clock = 92.8125MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
367 * 5'd10:rx3p clock = 88.75MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
368 * 5'd9:rx3p clock = 85.5MHz in rk628_combrxphy_set_hdmi_mode_for_cable()
[all …]
/OK3568_Linux_fs/u-boot/board/tbs/tbs2910/
H A Dtbs2910.c312 /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ in setup_display()
345 /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ in setup_display()
366 /* To enable AR8035 ouput a 125MHz clk from CLK_25M */ in ar8035_phy_fixup()
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-vt8500.c380 * Where O1 is 900MHz...3GHz;
381 * O2 is 600MHz >= (M * parent) / P >= 300MHz;
382 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
384 * D = 8: 37,5MHz...75MHz
385 * D = 4: 75MHz...150MHz
386 * D = 2: 150MHz...300MHz
387 * D = 1: 300MHz...600MHz
427 /* calculate frequency (MHz) after pre-divisor */ in wm8750_get_filter()
431 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", in wm8750_get_filter()
438 else if (freq >= 65) in wm8750_get_filter()

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