1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Shunqing Chen <csq@rock-chips.com>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset.h>
16 #include "rk628.h"
17 #include "rk628_combrxphy.h"
18 #include "rk628_cru.h"
19
20 #define COMBRXPHY_MAX_REGISTER COMBRX_REG(0x6790)
21
22 #define MAX_ROUND 6
23 #define MAX_DATA_NUM 16
24 #define MAX_CHANNEL 3
25 #define CLK_DET_TRY_TIMES 10
26 #define CHECK_CNT 100
27 #define CLK_STABLE_LOOP_CNT 10
28 #define CLK_STABLE_THRESHOLD 6
29
rk628_combrxphy_try_clk_detect(struct rk628 * rk628)30 static int rk628_combrxphy_try_clk_detect(struct rk628 *rk628)
31 {
32 u32 val, i;
33 int ret;
34
35 ret = -1;
36 rk628_control_assert(rk628, RGU_RXPHY);
37 usleep_range(10, 20);
38 rk628_control_deassert(rk628, RGU_RXPHY);
39 usleep_range(10, 20);
40
41 /* step1: set pin_rst_n to 1’b0.wait 1 period(1us).release reset */
42 /* step2: select pll clock src and enable auto check */
43 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val);
44 /* clear bit0 and bit3 */
45 val = val & 0xfffffff6;
46 rk628_i2c_write(rk628, COMBRX_REG(0x6630), val);
47 /* step3: select hdmi mode and enable chip, read reg6654,
48 * make sure auto setup done.
49 */
50 /* auto fsm reset related */
51 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val);
52 val = val | BIT(24);
53 rk628_i2c_write(rk628, COMBRX_REG(0x6630), val);
54 /* pull down ana rstn */
55 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
56 val = val & 0xfffffeff;
57 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
58 /* pull down dig rstn */
59 rk628_i2c_read(rk628, COMBRX_REG(0x66f4), &val);
60 val = val & 0xfffffffe;
61 rk628_i2c_write(rk628, COMBRX_REG(0x66f4), val);
62 /* pull up ana rstn */
63 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
64 val = val | 0x100;
65 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
66 /* pull up dig rstn */
67 rk628_i2c_read(rk628, COMBRX_REG(0x66f4), &val);
68 val = val | 0x1;
69 rk628_i2c_write(rk628, COMBRX_REG(0x66f4), val);
70
71 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
72 /* set bit0 and bit2 to 1*/
73 val = (val & 0xfffffff8) | 0x5;
74 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
75
76 /* auto fsm en = 0 */
77 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
78 /* set bit0 and bit2 to 1*/
79 val = (val & 0xfffffff8) | 0x4;
80 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
81
82 for (i = 0; i < 10; i++) {
83 mdelay(1);
84 rk628_i2c_read(rk628, COMBRX_REG(0x6654), &val);
85 if ((val & 0xf0000000) == 0x80000000) {
86 ret = 0;
87 dev_info(rk628->dev, "clock detected!\n");
88 break;
89 }
90 }
91
92 return ret;
93 }
94
rk628_combrxphy_get_data_of_round(struct rk628 * rk628,u32 * data)95 static void rk628_combrxphy_get_data_of_round(struct rk628 *rk628,
96 u32 *data)
97 {
98 u32 i;
99
100 for (i = 0; i < MAX_DATA_NUM; i++)
101 rk628_i2c_read(rk628, COMBRX_REG(0x6740 + i * 4), &data[i]);
102 }
103
rk628_combrxphy_set_dc_gain(struct rk628 * rk628,u32 x,u32 y,u32 z)104 static void rk628_combrxphy_set_dc_gain(struct rk628 *rk628,
105 u32 x, u32 y, u32 z)
106 {
107 u32 val;
108 u32 dc_gain_ch0, dc_gain_ch1, dc_gain_ch2;
109
110 dc_gain_ch0 = x & 0xf;
111 dc_gain_ch1 = y & 0xf;
112 dc_gain_ch2 = z & 0xf;
113 rk628_i2c_read(rk628, COMBRX_REG(0x661c), &val);
114
115 val = (val & 0xff0f0f0f) | (dc_gain_ch0 << 20) | (dc_gain_ch1 << 12) |
116 (dc_gain_ch2 << 4);
117 rk628_i2c_write(rk628, COMBRX_REG(0x661c), val);
118 }
119
rk628_combrxphy_set_data_of_round(u32 * data,u32 * data_in)120 static void rk628_combrxphy_set_data_of_round(u32 *data, u32 *data_in)
121 {
122 if ((data != NULL) && (data_in != NULL)) {
123 data_in[0] = data[0];
124 data_in[1] = data[7];
125 data_in[2] = data[13];
126 data_in[3] = data[14];
127 data_in[4] = data[15];
128 data_in[5] = data[1];
129 data_in[6] = data[2];
130 data_in[7] = data[3];
131 data_in[8] = data[4];
132 data_in[9] = data[5];
133 data_in[10] = data[6];
134 data_in[11] = data[8];
135 data_in[12] = data[9];
136 data_in[13] = data[10];
137 data_in[14] = data[11];
138 data_in[15] = data[12];
139 }
140 }
141
142 static void
rk628_combrxphy_max_zero_of_round(struct rk628 * rk628,u32 * data_in,u32 * max_zero,u32 * max_val,int n,int ch)143 rk628_combrxphy_max_zero_of_round(struct rk628 *rk628,
144 u32 *data_in, u32 *max_zero,
145 u32 *max_val, int n, int ch)
146 {
147 u32 i;
148 u32 cnt = 0;
149 u32 max_cnt = 0;
150 u32 max_v = 0;
151
152 for (i = 0; i < MAX_DATA_NUM; i++) {
153 if (max_v < data_in[i])
154 max_v = data_in[i];
155 }
156
157 for (i = 0; i < MAX_DATA_NUM; i++) {
158 if (data_in[i] == 0)
159 cnt = cnt + 200;
160 else if ((data_in[i] > 0) && (data_in[i] < 100))
161 cnt = cnt + 100 - data_in[i];
162 }
163 max_cnt = (cnt >= 3200) ? 0 : cnt;
164
165 max_zero[n] = max_cnt;
166 max_val[n] = max_v;
167 dev_info(rk628->dev, "channel:%d, round:%d, max_zero_cnt:%d, max_val:%#x\n",
168 ch, n, max_zero[n], max_val[n]);
169 }
170
rk628_combrxphy_chose_round_for_ch(struct rk628 * rk628,u32 * rd_max_zero,u32 * rd_max_val,int ch)171 static int rk628_combrxphy_chose_round_for_ch(struct rk628 *rk628,
172 u32 *rd_max_zero,
173 u32 *rd_max_val, int ch)
174 {
175 int i, rd = 0;
176 u32 max = 0;
177 u32 max_v = 0;
178
179 for (i = 0; i < MAX_ROUND; i++) {
180 if (rd_max_zero[i] > max) {
181 max = rd_max_zero[i];
182 max_v = rd_max_val[i];
183 rd = i;
184 } else if (rd_max_zero[i] == max && rd_max_val[i] > max_v) {
185 max = rd_max_zero[i];
186 max_v = rd_max_val[i];
187 rd = i;
188 }
189 }
190 dev_info(rk628->dev, "%s channel:%d, rd:%d\n", __func__, ch, rd);
191
192 return rd;
193 }
194
rk628_combrxphy_set_sample_edge_round(struct rk628 * rk628,u32 x,u32 y,u32 z)195 static void rk628_combrxphy_set_sample_edge_round(struct rk628 *rk628, u32 x, u32 y, u32 z)
196 {
197 u32 val;
198 u32 equ_gain_ch0, equ_gain_ch1, equ_gain_ch2;
199
200 equ_gain_ch0 = (x & 0xf);
201 equ_gain_ch1 = (y & 0xf);
202 equ_gain_ch2 = (z & 0xf);
203 rk628_i2c_read(rk628, COMBRX_REG(0x6618), &val);
204 val = (val & 0xff00f0ff) | (equ_gain_ch1 << 20) |
205 (equ_gain_ch0 << 16) | (equ_gain_ch2 << 8);
206 rk628_i2c_write(rk628, COMBRX_REG(0x6618), val);
207 }
208
rk628_combrxphy_start_sample_edge(struct rk628 * rk628)209 static void rk628_combrxphy_start_sample_edge(struct rk628 *rk628)
210 {
211 u32 val;
212
213 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
214 val &= 0xfffff1ff;
215 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
216 rk628_i2c_read(rk628, COMBRX_REG(0x66f0), &val);
217 val = (val & 0xfffff1ff) | (0x7 << 9);
218 rk628_i2c_write(rk628, COMBRX_REG(0x66f0), val);
219 }
220
rk628_combrxphy_set_sample_edge_mode(struct rk628 * rk628,int ch)221 static void rk628_combrxphy_set_sample_edge_mode(struct rk628 *rk628, int ch)
222 {
223 u32 val;
224
225 rk628_i2c_read(rk628, COMBRX_REG(0x6634), &val);
226 val = val & (~(0xf << ((ch + 1) * 4)));
227 rk628_i2c_write(rk628, COMBRX_REG(0x6634), val);
228 }
229
rk628_combrxphy_select_channel(struct rk628 * rk628,int ch)230 static void rk628_combrxphy_select_channel(struct rk628 *rk628, int ch)
231 {
232 u32 val;
233
234 rk628_i2c_read(rk628, COMBRX_REG(0x6700), &val);
235 val = (val & 0xfffffffc) | (ch & 0x3);
236 rk628_i2c_write(rk628, COMBRX_REG(0x6700), val);
237 }
238
rk628_combrxphy_cfg_6730(struct rk628 * rk628)239 static void rk628_combrxphy_cfg_6730(struct rk628 *rk628)
240 {
241 u32 val;
242
243 rk628_i2c_read(rk628, COMBRX_REG(0x6730), &val);
244 val = (val & 0xffff0000) | 0x1;
245 rk628_i2c_write(rk628, COMBRX_REG(0x6730), val);
246 }
247
rk628_combrxphy_sample_edge_procedure_for_cable(struct rk628 * rk628,u32 cdr_mode)248 static void rk628_combrxphy_sample_edge_procedure_for_cable(struct rk628 *rk628, u32 cdr_mode)
249 {
250 u32 n, ch;
251 u32 data[MAX_DATA_NUM];
252 u32 data_in[MAX_DATA_NUM];
253 u32 round_max_zero[MAX_CHANNEL][MAX_ROUND];
254 u32 round_max_value[MAX_CHANNEL][MAX_ROUND];
255 u32 ch_round[MAX_CHANNEL];
256 u32 edge, dc_gain;
257 u32 rd_offset;
258
259 /* Step1: set sample edge mode for channel 0~2 */
260 for (ch = 0; ch < MAX_CHANNEL; ch++)
261 rk628_combrxphy_set_sample_edge_mode(rk628, ch);
262
263 /* step2: once per round */
264 for (ch = 0; ch < MAX_CHANNEL; ch++) {
265 rk628_combrxphy_select_channel(rk628, ch);
266 rk628_combrxphy_cfg_6730(rk628);
267 }
268
269 /* step3: config sample edge until the end of one frame
270 * (for example 1080p:2200*1125=32’h25c3f8)
271 */
272 if (cdr_mode < 16) {
273 dc_gain = 0;
274 rd_offset = 0;
275 } else if (cdr_mode < 18) {
276 dc_gain = 1;
277 rd_offset = 0;
278 } else {
279 dc_gain = 3;
280 rd_offset = 2;
281 }
282
283 /* When the pix clk is the same, the low frame rate resolution is used
284 * to calculate the sampling window (the frame rate is not less than
285 * 30). The sampling delay time is configured as 40ms.
286 */
287 if (cdr_mode <= 1) { /* 27M vic17 720x576P50 */
288 edge = 864 * 625;
289 } else if (cdr_mode <= 4) { /* 59.4M vic81 1680x720P30 */
290 edge = 2640 * 750;
291 } else if (cdr_mode <= 7) { /* 74.25M vic34 1920x1080P30 */
292 edge = 2200 * 1125;
293 } else if (cdr_mode <= 14) { /* 119M vic88 2560x1180P30 */
294 edge = 3520 * 1125;
295 } else if (cdr_mode <= 16) { /* 148.5M vic31 1920x1080P50 */
296 edge = 2640 * 1125;
297 } else if (cdr_mode <= 17) { /* 162M vic89 2560x1080P50 */
298 edge = 3300 * 1125;
299 } else if (cdr_mode <= 18) { /* 297M vic95 3840x2160P30 */
300 edge = 4400 * 2250;
301 } else { /* unkonw vic16 1920x1080P60 */
302 edge = 2200 * 1125;
303 }
304
305 dev_info(rk628->dev, "cdr_mode:%d, dc_gain:%d, rd_offset:%d, edge:%#x\n",
306 cdr_mode, dc_gain, rd_offset, edge);
307 for (ch = 0; ch < MAX_CHANNEL; ch++) {
308 rk628_combrxphy_select_channel(rk628, ch);
309 rk628_i2c_write(rk628, COMBRX_REG(0x6708), edge);
310 }
311
312 rk628_combrxphy_set_dc_gain(rk628, dc_gain, dc_gain, dc_gain);
313 for (n = rd_offset; n < (rd_offset + MAX_ROUND); n++) {
314 /* step4:set sample edge round value n,n=0(n=0~31) */
315 rk628_combrxphy_set_sample_edge_round(rk628, n, n, n);
316 /* step5:start sample edge */
317 rk628_combrxphy_start_sample_edge(rk628);
318 /* step6:waiting more than one frame time */
319 mdelay(41);
320 for (ch = 0; ch < MAX_CHANNEL; ch++) {
321 /* step7: get data of round n */
322 rk628_combrxphy_select_channel(rk628, ch);
323 rk628_combrxphy_get_data_of_round(rk628, data);
324 rk628_combrxphy_set_data_of_round(data, data_in);
325 /* step8: get the max constant value of round n */
326 rk628_combrxphy_max_zero_of_round(rk628, data_in,
327 round_max_zero[ch], round_max_value[ch],
328 n - rd_offset, ch);
329 }
330 }
331
332 /* step9: after finish round, get the max constant value and
333 * corresponding value n.
334 */
335 for (ch = 0; ch < MAX_CHANNEL; ch++) {
336 ch_round[ch] =
337 rk628_combrxphy_chose_round_for_ch(rk628, round_max_zero[ch],
338 round_max_value[ch], ch) + rd_offset;
339 }
340 dev_info(rk628->dev, "last equ gain ch0:%d, ch1:%d, ch2:%d\n",
341 ch_round[0], ch_round[1], ch_round[2]);
342
343 /* step10: write result to sample edge round value */
344 rk628_combrxphy_set_sample_edge_round(rk628, ch_round[0], ch_round[1], ch_round[2]);
345
346 /* do step5, step6 again */
347 /* step5:start sample edge */
348 rk628_combrxphy_start_sample_edge(rk628);
349 /* step6:waiting more than one frame time */
350 mdelay(41);
351 }
352
rk628_combrxphy_set_hdmi_mode_for_cable(struct rk628 * rk628,int f)353 static int rk628_combrxphy_set_hdmi_mode_for_cable(struct rk628 *rk628, int f)
354 {
355 u32 val, val_a, val_b, data_a, data_b;
356 u32 i, j, count, ret;
357 u32 cdr_mode, cdr_data, pll_man;
358 u32 tmds_bitrate_per_lane;
359 u32 cdr_data_min, cdr_data_max;
360 u32 temp = 0;
361 u32 state, channel_st;
362
363 /*
364 * use the mode of automatic clock detection, only supports fixed TMDS
365 * frequency.Refer to register 0x6654[21:16]:
366 * 5'd31:Error mode
367 * 5'd30:manual mode detected
368 * 5'd18:rx3p clock = 297MHz
369 * 5'd17:rx3p clock = 162MHz
370 * 5'd16:rx3p clock = 148.5MHz
371 * 5'd15:rx3p clock = 135MHz
372 * 5'd14:rx3p clock = 119MHz
373 * 5'd13:rx3p clock = 108MHz
374 * 5'd12:rx3p clock = 101MHz
375 * 5'd11:rx3p clock = 92.8125MHz
376 * 5'd10:rx3p clock = 88.75MHz
377 * 5'd9:rx3p clock = 85.5MHz
378 * 5'd8:rx3p clock = 83.5MHz
379 * 5'd7:rx3p clock = 74.25MHz
380 * 5'd6:rx3p clock = 68.25MHz
381 * 5'd5:rx3p clock = 65MHz
382 * 5'd4:rx3p clock = 59.4MHz
383 * 5'd3:rx3p clock = 40MHz
384 * 5'd2:rx3p clock = 33.75MHz
385 * 5'd1:rx3p clock = 27MHz
386 * 5'd0:rx3p clock = 25.17MHz
387 */
388
389 const u32 cdr_mode_to_khz[] = {
390 25170, 27000, 33750, 40000, 59400, 65000, 68250,
391 74250, 83500, 85500, 88750, 92812, 101000, 108000,
392 119000, 135000, 148500, 162000, 297000,
393 };
394
395 for (i = 0; i < CLK_DET_TRY_TIMES; i++) {
396 rk628_i2c_read(rk628, COMBRX_REG(0x6620), &val);
397 if (!temp && val) {
398 temp = val;
399 msleep(200);
400 }
401 if (rk628_combrxphy_try_clk_detect(rk628) >= 0)
402 break;
403 mdelay(1);
404 }
405 rk628_i2c_read(rk628, COMBRX_REG(0x6654), &val);
406 dev_info(rk628->dev, "clk det over cnt:%d, reg_0x6654:%#x\n", i, val);
407 state = (val >> 28) & 0xf;
408 if (state == 5) {
409 dev_info(rk628->dev, "Clock detection anomaly\n");
410 } else if (state == 4) {
411 channel_st = (val >> 21) & 0x7f;
412 dev_info(rk628->dev, "%s%s%s%s%s%s%s%s level detection anomaly\n",
413 channel_st & 0x40 ? "|clk_p|" : "",
414 channel_st & 0x20 ? "|clk_n|" : "",
415 channel_st & 0x10 ? "|d0_p|" : "",
416 channel_st & 0x08 ? "|d0_n|" : "",
417 channel_st & 0x04 ? "|d1_p|" : "",
418 channel_st & 0x02 ? "|d1_n|" : "",
419 channel_st & 0x01 ? "|d2_p|" : "",
420 channel_st ? "" : "|d2_n|");
421 }
422
423 rk628_i2c_read(rk628, COMBRX_REG(0x6620), &val);
424 if ((i == CLK_DET_TRY_TIMES) ||
425 ((val & 0x7f000000) == 0) ||
426 ((val & 0x007f0000) == 0) ||
427 ((val & 0x00007f00) == 0) ||
428 ((val & 0x0000007f) == 0)) {
429 dev_info(rk628->dev, "clock detected failed, cfg resistance manual!\n");
430 rk628_i2c_write(rk628, COMBRX_REG(0x6620), 0x66666666);
431 rk628_i2c_update_bits(rk628, COMBRX_REG(0x6604), BIT(31), BIT(31));
432 mdelay(1);
433 }
434
435 /* step4: get cdr_mode and cdr_data */
436 for (j = 0; j < CLK_STABLE_LOOP_CNT ; j++) {
437 cdr_data_min = 0xffffffff;
438 cdr_data_max = 0;
439
440 for (i = 0; i < CLK_DET_TRY_TIMES; i++) {
441 rk628_i2c_read(rk628, COMBRX_REG(0x6654), &val);
442 cdr_data = val & 0xffff;
443 if (cdr_data <= cdr_data_min)
444 cdr_data_min = cdr_data;
445 if (cdr_data >= cdr_data_max)
446 cdr_data_max = cdr_data;
447 udelay(50);
448 }
449
450 if (((cdr_data_max - cdr_data_min) <= CLK_STABLE_THRESHOLD) &&
451 (cdr_data_min >= 60)) {
452 dev_info(rk628->dev, "clock stable!");
453 break;
454 }
455 }
456
457 if (j == CLK_STABLE_LOOP_CNT) {
458 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val_a);
459 rk628_i2c_read(rk628, COMBRX_REG(0x6608), &val_b);
460 dev_err(rk628->dev,
461 "clk not stable, reg_0x6630:%#x, reg_0x6608:%#x",
462 val_a, val_b);
463 /* bypass level detection anomaly */
464 if (state == 4)
465 rk628_i2c_update_bits(rk628, COMBRX_REG(0x6628), BIT(31), BIT(31));
466 else
467 return -EINVAL;
468 }
469
470 rk628_i2c_read(rk628, COMBRX_REG(0x6654), &val);
471 if ((val & 0x1f0000) == 0x1f0000) {
472 rk628_i2c_read(rk628, COMBRX_REG(0x6630), &val_a);
473 rk628_i2c_read(rk628, COMBRX_REG(0x6608), &val_b);
474 dev_err(rk628->dev,
475 "clock error: 0x1f, reg_0x6630:%#x, reg_0x6608:%#x",
476 val_a, val_b);
477
478 return -EINVAL;
479 }
480
481 cdr_mode = (val >> 16) & 0x1f;
482 cdr_data = val & 0xffff;
483 dev_info(rk628->dev, "cdr_mode:%d, cdr_data:%d\n", cdr_mode, cdr_data);
484
485 /* step5: manually configure PLL
486 * cfg reg 66a8 tmds clock div2 for rgb/yuv444 as default
487 * reg 662c[16:8] pll_pre_div
488 */
489 if (f <= 340000) {
490 rk628_i2c_write(rk628, COMBRX_REG(0x662c), 0x01000500);
491 rk628_i2c_write(rk628, COMBRX_REG(0x66a8), 0x0000c600);
492 } else {
493 rk628_i2c_write(rk628, COMBRX_REG(0x662c), 0x01001400);
494 rk628_i2c_write(rk628, COMBRX_REG(0x66a8), 0x0000c600);
495 }
496
497 /* when tmds bitrate/lane <= 340M, bitrate/lane = pix_clk * 10 */
498 tmds_bitrate_per_lane = cdr_mode_to_khz[cdr_mode] * 10;
499 if (tmds_bitrate_per_lane < 400000)
500 pll_man = 0x7960c;
501 else if (tmds_bitrate_per_lane < 600000)
502 pll_man = 0x7750c;
503 else if (tmds_bitrate_per_lane < 800000)
504 pll_man = 0x7964c;
505 else if (tmds_bitrate_per_lane < 1000000)
506 pll_man = 0x7754c;
507 else if (tmds_bitrate_per_lane < 1600000)
508 pll_man = 0x7a108;
509 else if (tmds_bitrate_per_lane < 2400000)
510 pll_man = 0x73588;
511 else if (tmds_bitrate_per_lane < 3400000)
512 pll_man = 0x7a108;
513 else
514 pll_man = 0x7f0c8;
515
516 dev_info(rk628->dev, "cdr_mode:%d, pll_man:%#x\n", cdr_mode, pll_man);
517 rk628_i2c_write(rk628, COMBRX_REG(0x6630), pll_man);
518
519 /* step6: EQ and SAMPLE cfg */
520 rk628_combrxphy_sample_edge_procedure_for_cable(rk628, cdr_mode);
521
522 /* step7: Deassert fifo reset,enable fifo write and read */
523 /* reset rx_infifo */
524 rk628_i2c_write(rk628, COMBRX_REG(0x66a0), 0x00000003);
525 /* rx_infofo wr/rd disable */
526 rk628_i2c_write(rk628, COMBRX_REG(0x66b0), 0x00080060);
527 /* deassert rx_infifo reset */
528 rk628_i2c_write(rk628, COMBRX_REG(0x66a0), 0x00000083);
529 /* enable rx_infofo wr/rd en */
530 rk628_i2c_write(rk628, COMBRX_REG(0x66b0), 0x00380060);
531 /* cfg 0x2260 high_8b to 0x66ac high_8b, low_8b to 0x66b0 low_8b */
532 rk628_i2c_update_bits(rk628, COMBRX_REG(0x66ac), GENMASK(31, 24), UPDATE(0x22, 31, 24));
533 mdelay(6);
534
535 /* step8: check all 3 data channels alignment */
536 count = 0;
537 for (i = 0; i < CHECK_CNT; i++) {
538 mdelay(1);
539 rk628_i2c_read(rk628, COMBRX_REG(0x66b4), &data_a);
540 rk628_i2c_read(rk628, COMBRX_REG(0x66b8), &data_b);
541 /* ch0 ch1 ch2 lock */
542 if (((data_a & 0x00ff00ff) == 0x00ff00ff) &&
543 ((data_b & 0xff) == 0xff)) {
544 count++;
545 }
546 }
547
548 if (count >= CHECK_CNT) {
549 dev_info(rk628->dev, "channel alignment done\n");
550 dev_info(rk628->dev, "rx initial done\n");
551 ret = 0;
552 } else if (count > 0) {
553 dev_info(rk628->dev, "link not stable, count:%d of 100\n", count);
554 ret = 0;
555 } else {
556 dev_err(rk628->dev, "channel alignment failed!\n");
557 ret = -EINVAL;
558 }
559
560 return ret;
561 }
562
rk628_rxphy_power_on(struct rk628 * rk628,int f)563 int rk628_rxphy_power_on(struct rk628 *rk628, int f)
564 {
565 rk628_control_assert(rk628, RGU_RXPHY);
566 udelay(10);
567 rk628_control_deassert(rk628, RGU_RXPHY);
568 udelay(10);
569
570 f = f & 0x7fffffff;
571 return rk628_combrxphy_set_hdmi_mode_for_cable(rk628, f);
572 }
573 EXPORT_SYMBOL(rk628_rxphy_power_on);
574
rk628_rxphy_power_off(struct rk628 * rk628)575 int rk628_rxphy_power_off(struct rk628 *rk628)
576 {
577 rk628_i2c_update_bits(rk628, COMBRX_REG(0x6630), BIT(0), BIT(0));
578 rk628_control_assert(rk628, RGU_RXPHY);
579 udelay(10);
580
581 return 0;
582 }
583 EXPORT_SYMBOL(rk628_rxphy_power_off);
584