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/OK3568_Linux_fs/kernel/arch/nios2/mm/
H A Dtlb.c22 ((((1UL << (cpuinfo.tlb_ptr_sz - cpuinfo.tlb_num_ways_log2))) - 1) \
38 return ((addr | 0xC0000000UL) >> PAGE_SHIFT) << 2; in pteaddr_invalid()
47 unsigned int way; in replace_tlb_one_pid() local
50 /* remember pid/way until we return. */ in replace_tlb_one_pid()
53 WRCTL(CTL_PTEADDR, (addr >> PAGE_SHIFT) << 2); in replace_tlb_one_pid()
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in replace_tlb_one_pid()
60 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
64 if (((pteaddr >> 2) & 0xfffff) != (addr >> PAGE_SHIFT)) in replace_tlb_one_pid()
73 (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
90 pr_debug("Flush tlb-entry for vaddr=%#lx\n", addr); in flush_tlb_one_pid()
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/OK3568_Linux_fs/kernel/arch/x86/kernel/cpu/
H A Dcacheinfo.c1 // SPDX-License-Identifier: GPL-2.0
27 #define LVL_1_DATA 2
45 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
46 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
48 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
49 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
50 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
51 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
52 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
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H A Dintel.c1 // SPDX-License-Identifier: GPL-2.0
18 #include <asm/intel-family.h>
61 * Processors which have self-snooping capability can handle conflicting
69 switch (c->x86_model) { in check_memory_type_self_snoop_errata()
101 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
103 switch (c->x86_model) { in probe_xeon_phi_r3mwait()
125 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
126 * - https://kb.vmware.com/s/article/52345
127 * - Microcode revisions observed in the wild
128 * - Release note from 20180108 microcode release
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S2 * SPDX-License-Identifier: GPL-2.0+
21 * Flush the whole D-cache.
23 * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
25 * Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
31 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
39 cmp r1, #2 @ see what cache we have at this level
40 blt skip @ skip if no cache, or just i-cache
41 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
47 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
48 clz r5, r4 @ find bit position of way size increment
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/OK3568_Linux_fs/kernel/arch/openrisc/include/asm/
H A Dspr_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
19 /* Definition of special-purpose registers (SPRs). */
29 #define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
43 #define SPR_CPUCFGR (SPRGROUP_SYS + 2)
71 #define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dbcm2837.dtsi2 #include "bcm2835-common.dtsi"
3 #include "bcm2835-rpi-common.dtsi"
11 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
14 compatible = "brcm,bcm2836-l1-intc";
16 interrupt-controller;
17 #interrupt-cells = <2>;
18 interrupt-parent = <&local_intc>;
22 arm-pmu {
23 compatible = "arm,cortex-a53-pmu";
24 interrupt-parent = <&local_intc>;
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/OK3568_Linux_fs/kernel/arch/x86/crypto/
H A Dtwofish_glue_3way.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Glue Code for 3-way parallel assembler optimized version of Twofish
25 return twofish_setkey(&tfm->base, key, keylen); in twofish_setkey_skcipher()
41 u128 ivs[2]; in twofish_dec_blk_cbc_3way()
51 u128_xor(&dst[2], &dst[2], &ivs[1]); in twofish_dec_blk_cbc_3way()
81 dst[2] = src[2]; in twofish_enc_blk_ctr_3way()
88 le128_to_be128(&ctrblks[2], iv); in twofish_enc_blk_ctr_3way()
96 .num_funcs = 2,
97 .fpu_blocks_limit = -1,
109 .num_funcs = 2,
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/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A De300.h15 * Hardware Implementation-Dependent Register 0 (HID0)
77 * Hardware Implementation-Dependent Register 2 (HID2)
84 #define HID2_IWLCK_001 0x00002000 /* way 0 locked */
85 #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
86 #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
87 #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
88 #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
89 #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
/OK3568_Linux_fs/kernel/arch/mips/kernel/
H A Dbmips_5xxx_init.S7 * Copyright (C) 2011-2012 by Broadcom Corporation
34 addiu t1, t1, -1 ; \
64 #define CP0_DCACHE_TAG_LO $28, 2
68 #define CP0_DCACHE_TAG_HI $29, 2
84 #define BRCM_ZSC_REQ_BUFFER_REG 2 << 3
107 .align 2
112 * Description: compute the I-cache size and I-cache line size
126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
131 * vi) 0x5 - 0x7: Reserved.
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/OK3568_Linux_fs/kernel/arch/arc/mm/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Reintroduce duplicate PD fixup - some customer chips still have the issue
11 * -No need to flush_cache_page( ) for each call to update_mmu_cache()
13 * = page-fault thrice as fast (75 usec to 28 usec)
18 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22 * -MMU v2/v3 BCRs decoded differently
23 * -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
24 * -tlb_entry_erase( ) can be void
25 * -local_flush_tlb_range( ):
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/OK3568_Linux_fs/kernel/arch/powerpc/mm/nohash/
H A Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
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/OK3568_Linux_fs/kernel/arch/arm/mm/
H A Dcache-xsc3l2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
51 __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way)); in xsc3_l2_inv_all()
61 if (va != -1) in l2_unmap_va()
70 unsigned long pa_offset = pa << (32 - PAGE_SHIFT); in l2_map_va()
71 if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { in l2_map_va()
80 return va + (pa_offset >> (32 - PAGE_SHIFT)); in l2_map_va()
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H A Dcache-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7m.S
5 * Based on linux/arch/arm/mm/cache-v7.S
19 #include "proc-macros.S"
48 * dcisw: Invalidate data cache by set/way
55 * dccisw: Clean and invalidate data cache by set/way
129 and r3, r1, r0, lsr #3 @ NumWays - 1
137 1: sub r2, r2, #1 @ NumSets--
139 2: subs r3, r3, #1 @ Temp--
144 bgt 2b
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/OK3568_Linux_fs/kernel/Documentation/admin-guide/
H A Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
7 2 = /dev/kmem Kernel virtual memory access
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
49 2 block Floppy disks
52 2 = /dev/fd2 Controller 0, drive 2, autodetect
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/OK3568_Linux_fs/kernel/arch/mips/mm/
H A Dcerr-sb1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)
73 printk(" multiple-buserr"); in breakout_errctl()
80 printk(" tag-parity"); in breakout_cerri()
82 printk(" data-parity"); in breakout_cerri()
114 printk(" multi-err"); in breakout_cerrd()
116 printk(" tag-state"); in breakout_cerrd()
118 printk(" tag-address"); in breakout_cerrd()
120 printk(" data-SBE"); in breakout_cerrd()
122 printk(" data-DBE"); in breakout_cerrd()
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/OK3568_Linux_fs/kernel/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h7 * Copyright (c) 2003-2017 Cavium, Inc.
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
44 #define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
52 /* Number of L2C Tag-and-data sections (TADs) that are connected to LMC. */
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
131 CVMX_L2C_TAD_EVENT_TAG_MISS = 2,
183 * Return the L2 Cache way partitioning for a given core.
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/OK3568_Linux_fs/kernel/arch/powerpc/platforms/powernv/
H A Dsubcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 * A core can be in one of three states, unsplit, 2-way split, and 4-way split.
35 * ------------|------------------
37 * 2-way split | 2
38 * 4-way split | 4
44 * ----------------------------
46 * ----------------------------
47 * Thread | 0 1 2 3 4 5 6 7 |
48 * ----------------------------
50 * 2-way split:
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/OK3568_Linux_fs/external/chromium/licenses/
H A DNOTICE24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 -------------------------------------------------------------------
29 strchr - find a character in a string
55 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
58 -------------------------------------------------------------------
68 2. Redistributions in binary form must reproduce the above copyright
83 ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
86 -------------------------------------------------------------------
96 -------------------------------------------------------------------
109 2. Redistributions in binary form must reproduce the above copyright
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mux/
H A Dmux-controller.txt11 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
12 0-7 for an 8-way multiplexer, etc.
16 ---------
19 want to use with a property containing a 'mux-ctrl-list':
21 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
22 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
23 mux-ctrl-phandle : phandle to mux controller node
24 mux-ctrl-specifier : array of #mux-control-cells specifying the
27 Mux controller properties should be named "mux-controls". The exact meaning of
29 each consumer. An optional property "mux-control-names" may contain a list of
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/OK3568_Linux_fs/kernel/arch/arm/include/asm/
H A Dv7m.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 #define V7M_SCB_AIRCR_SYSRESETREQ (1 << 2)
24 #define V7M_SCB_SCR_SLEEPDEEP (1 << 2)
48 * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
49 * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
52 #define EXC_RET_THREADMODE_PROCESSSTACK (3 << 2)
61 /* Memory-mapped MPU registers for M-class */
65 #define MPU_CTRL_PRIVDEFENA (1 << 2)
80 #define V7M_SCB_ICIALLU 0x250 /* I-cache invalidate all to PoU */
81 #define V7M_SCB_ICIMVAU 0x258 /* I-cache invalidate by MVA to PoU */
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/OK3568_Linux_fs/u-boot/doc/
H A DREADME.N12137 - 16-/32-bit mixable instruction format.
8 - 32 general-purpose 32-bit registers.
9 - 8-stage pipeline.
10 - Dynamic branch prediction.
11 - 32/64/128/256 BTB.
12 - Return address stack (RAS).
13 - Vector interrupts for internal/external.
15 - 3 HW-level nested interruptions.
16 - User and super-user mode support.
17 - Memory-mapped I/O.
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/OK3568_Linux_fs/kernel/arch/arc/include/asm/
H A Dtlb-mmu1.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
20 ; Calculate set index for 2-way MMU
21 ; -avoiding use of GetIndex from MMU
22 ; and its unpleasant LFSR pseudo-random sequence
26 ; -- jh_ex_way_set not cleared on startup
30 ; -- should be in cache since in same line
38 or.nz r0,r0,1 ; set way bit
44 ; JH hack #2
45 ; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
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/OK3568_Linux_fs/kernel/arch/mips/cavium-octeon/executive/
H A Dcvmx-l2c.c7 * Copyright (c) 2003-2017 Cavium, Inc.
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Implementation of the Level 2 Cache (L2C) control,
36 #include <asm/octeon/cvmx-l2c.h>
37 #include <asm/octeon/cvmx-spinlock.h>
43 * NOTE: This only protects calls from within a single application -
55 return -1; in cvmx_l2c_get_core_way_partition()
89 valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1; in cvmx_l2c_set_core_way_partition()
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/OK3568_Linux_fs/kernel/arch/xtensa/include/asm/
H A Dtlbflush.h6 * Copyright (C) 2001 - 2013 Tensilica Inc.
27 * - flush_tlb_all() flushes all processes TLB entries
28 * - flush_tlb_mm(mm) flushes the specified mm context TLB entries
29 * - flush_tlb_page(mm, vmaddr) flushes a single page
30 * - flush_tlb_range(mm, start, end) flushes a range of pages
130 static inline void write_dtlb_entry (pte_t entry, int way) in write_dtlb_entry() argument
133 : : "r" (way), "r" (entry) ); in write_dtlb_entry()
136 static inline void write_itlb_entry (pte_t entry, int way) in write_itlb_entry() argument
139 : : "r" (way), "r" (entry) ); in write_itlb_entry()
146 invalidate_dtlb_entry (DTLB_WAY_PGD+2); in invalidate_page_directory()
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/OK3568_Linux_fs/kernel/arch/sh/mm/
H A Dcache-sh2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2.c
23 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
24 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2__flush_wback_region()
25 & ~(L1_CACHE_BYTES-1); in sh2__flush_wback_region()
28 int way; in sh2__flush_wback_region() local
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
30 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
33 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
44 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2__flush_purge_region()
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