1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2004 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * Liberty Eran (liberty@freescale.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __E300_H__ 7*4882a593Smuzhiyun #define __E300_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define PVR_E300C1 0x80830000 10*4882a593Smuzhiyun #define PVR_E300C2 0x80840000 11*4882a593Smuzhiyun #define PVR_E300C3 0x80850000 12*4882a593Smuzhiyun #define PVR_E300C4 0x80860000 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Hardware Implementation-Dependent Register 0 (HID0) 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* #define HID0 1008 already defined in processor.h */ 19*4882a593Smuzhiyun #define HID0_MASK_MACHINE_CHECK 0x00000000 20*4882a593Smuzhiyun #define HID0_ENABLE_MACHINE_CHECK 0x80000000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define HID0_DISABLE_CACHE_PARITY 0x00000000 23*4882a593Smuzhiyun #define HID0_ENABLE_CACHE_PARITY 0x40000000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ 26*4882a593Smuzhiyun #define HID0_ENABLE_ADDRESS_PARITY 0x20000000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ 29*4882a593Smuzhiyun #define HID0_ENABLE_DATE_PARITY 0x10000000 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define HID0_CORE_CLK_OUT 0x00000000 32*4882a593Smuzhiyun #define HID0_CORE_CLK_OUT_DIV_2 0x08000000 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ 35*4882a593Smuzhiyun #define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define HID0_DISABLE_DOSE_MODE 0x00000000 38*4882a593Smuzhiyun #define HID0_ENABLE_DOSE_MODE 0x00800000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define HID0_DISABLE_NAP_MODE 0x00000000 41*4882a593Smuzhiyun #define HID0_ENABLE_NAP_MODE 0x00400000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define HID0_DISABLE_SLEEP_MODE 0x00000000 44*4882a593Smuzhiyun #define HID0_ENABLE_SLEEP_MODE 0x00200000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 47*4882a593Smuzhiyun #define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define HID0_SOFT_RESET 0x00010000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 52*4882a593Smuzhiyun #define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define HID0_DISABLE_DATA_CACHE 0x00000000 55*4882a593Smuzhiyun #define HID0_ENABLE_DATA_CACHE 0x00004000 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define HID0_LOCK_DATA_CACHE 0x00001000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define HID0_INVALIDATE_DATA_CACHE 0x00000400 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define HID0_DISABLE_M_BIT 0x00000000 66*4882a593Smuzhiyun #define HID0_ENABLE_M_BIT 0x00000080 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define HID0_FBIOB 0x00000010 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 71*4882a593Smuzhiyun #define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 74*4882a593Smuzhiyun #define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* 77*4882a593Smuzhiyun * Hardware Implementation-Dependent Register 2 (HID2) 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun #define HID2 1011 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define HID2_LET 0x08000000 82*4882a593Smuzhiyun #define HID2_HBE 0x00040000 83*4882a593Smuzhiyun #define HID2_IWLCK_000 0x00000000 /* no ways locked */ 84*4882a593Smuzhiyun #define HID2_IWLCK_001 0x00002000 /* way 0 locked */ 85*4882a593Smuzhiyun #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */ 86*4882a593Smuzhiyun #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */ 87*4882a593Smuzhiyun #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */ 88*4882a593Smuzhiyun #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ 89*4882a593Smuzhiyun #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* __E300_H__ */ 92