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/OK3568_Linux_fs/external/xserver/debian/patches/
H A D001_fedora_extramodes.patch18 +# 1152x864 @ 60.00 Hz (GTF) hsync: 53.70 kHz; pclk: 81.62 MHz
21 +# 1152x864 @ 70.00 Hz (GTF) hsync: 63.00 kHz; pclk: 96.77 MHz
24 +# 1152x864 @ 75.00 Hz (GTF) hsync: 67.65 kHz; pclk: 104.99 MHz
27 +# 1152x864 @ 85.00 Hz (GTF) hsync: 77.10 kHz; pclk: 119.65 MHz
33 +# 1152x864 @ 100.00 Hz (GTF) hsync: 91.50 kHz; pclk: 143.47 MHz
36 +# 1360x768 59.96 Hz (CVT) hsync: 47.37 kHz; pclk: 72.00 MHz
39 +# 1360x768 59.80 Hz (CVT) hsync: 47.72 kHz; pclk: 84.75 MHz
42 # 1400x1050 @ 60Hz (VESA GTF) hsync: 65.5kHz
43 ModeLine "1400x1050" 122.0 1400 1488 1640 1880 1050 1052 1064 1082 +hsync +vsync
45 +# 1400x1050 @ 70.00 Hz (GTF) hsync: 76.51 kHz; pclk: 145.06 MHz
[all …]
/OK3568_Linux_fs/external/xserver/hw/xfree86/common/
H A Dextramodes10 # 1400x1050 @ 60Hz (VESA GTF) hsync: 65.5kHz
11 ModeLine "1400x1050" 122.0 1400 1488 1640 1880 1050 1052 1064 1082 +hsync +vsync
13 # 1400x1050 @ 75Hz (VESA GTF) hsync: 82.2kHz
14 ModeLine "1400x1050" 155.8 1400 1464 1784 1912 1050 1052 1064 1090 +hsync +vsync
30 # 640x360 59.32 Hz (CVT 0.23M9-R) hsync: 22.19 kHz; pclk: 17.75 MHz
33 # 640x360 59.84 Hz (CVT 0.23M9) hsync: 22.50 kHz; pclk: 18.00 MHz
36 # 720x405 58.99 Hz (CVT 0.29M9-R) hsync: 24.72 kHz; pclk: 21.75 MHz
39 # 720x405 59.51 Hz (CVT 0.29M9) hsync: 25.11 kHz; pclk: 22.50 MHz
42 # 864x486 59.57 Hz (CVT 0.42M9-R) hsync: 29.79 kHz; pclk: 30.50 MHz
45 # 864x486 59.92 Hz (CVT 0.42M9) hsync: 30.32 kHz; pclk: 32.50 MHz
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c67 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
68 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
69 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
70 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
75 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
76 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
77 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
78 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
79 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
H A Dspeedstep-centrino.c83 frequency/voltage operating point; frequency in MHz, volts in mV.
85 #define OP(mhz, mv) \ argument
87 .frequency = (mhz) * 1000, \
88 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
98 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
107 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
159 OP(1400, 1484),
170 OP(1400, 1452),
182 OP(1400, 1420),
194 OP(1400, 1308),
[all …]
H A Dpowernow-k8.h89 * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
91 * - the parts can only step at <= 200 MHz intervals, odd fid values are
101 #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/t102xqds/
H A Dt1024_sd_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_nand_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A Dt1024_spi_rcw.cfg1 # single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
2 # Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
H A DREADME114 - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
115 - Software programmable in 1 MHz increments from 1-200 MHz.
118 - 100 MHz, 125 MHz and 156.25 MHz options.
119 - Spread-spectrum option for 100 MHz.
196 0x6F 100MHz 125MHz 1101
197 0xD6 100MHz 100MHz 1111
198 0x99 156.25MHz 100MHz 1011
204 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
205 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
206 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
/OK3568_Linux_fs/u-boot/arch/arm/mach-keystone/include/mach/
H A Dclock-k2l.h41 /* k2l DEV supports 800, 1000, 1200 MHz */
43 /* k2l ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
H A Dclock-k2hk.h44 /* k2h DEV supports 800, 1000, 1200 MHz */
46 /* k2h ARM supportd 800, 1000, 1200, 1350, 1400 MHz */
H A Dclock-k2e.h31 /* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */
/OK3568_Linux_fs/u-boot/board/freescale/t102xrdb/
H A Dt1024_sd_rcw.cfg4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
H A Dt1024_spi_rcw.cfg4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
H A Dt1024_nand_rcw.cfg4 #Core/DDR: 1400Mhz/1600MT/s with single source clock
H A DREADME179 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
180 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
181 Bin3: 1000MHz 1600MT/s 400MHz 500MHz
/OK3568_Linux_fs/u-boot/board/freescale/t208xqds/
H A Dddr.h29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
32 {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a},
49 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rv1126.h12 #define MHz 1000000 macro
14 #define OSC_HZ (24 * MHz)
17 #define APLL_HZ (1008 * MHz)
19 #define APLL_HZ (816 * MHz)
21 #define GPLL_HZ (1188 * MHz)
22 #define CPLL_HZ (500 * MHz)
23 #define HPLL_HZ (1400 * MHz)
24 #define PCLK_PDPMU_HZ (100 * MHz)
26 #define ACLK_PDBUS_HZ (396 * MHz)
28 #define ACLK_PDBUS_HZ (500 * MHz)
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/
H A Dexynos5433-tmu.dtsi56 /* Set maximum frequency as 1800MHz */
62 /* Set maximum frequency as 1700MHz */
68 /* Set maximum frequency as 1600MHz */
74 /* Set maximum frequency as 1500MHz */
80 /* Set maximum frequency as 1400MHz */
86 /* Set maximum frequencyas 1200MHz */
92 /* Set maximum frequency as 1000MHz */
230 /* Set maximum frequency as 1200MHz */
236 /* Set maximum frequency as 1100MHz */
242 /* Set maximum frequency as 1000MHz */
[all …]
/OK3568_Linux_fs/u-boot/board/renesas/stout/
H A Dstout.c48 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) in s_init()
85 * SD0 clock is set to 97.5MHz by default. in board_early_init_f()
86 * Set SD2 to the 97.5MHz as well. in board_early_init_f()
/OK3568_Linux_fs/u-boot/board/renesas/lager/
H A Dlager.c46 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) in s_init()
87 * SD0 clock is set to 97.5MHz by default. in board_early_init_f()
88 * Set SD2 to the 97.5MHz as well. in board_early_init_f()
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_mipi.c222 {1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c} in rk_mipi_phy_enable()
234 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; in rk_mipi_phy_enable()
245 if (ddr_clk / (MHz) >= freq_rang[i][0]) in rk_mipi_phy_enable()
259 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz in rk_mipi_phy_enable()
262 max_prediv = (refclk / (5 * MHz)); in rk_mipi_phy_enable()
263 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1); in rk_mipi_phy_enable()
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Ddm814x-clocks.dtsi209 /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */
275 /* L4_HS 220 MHz*/
293 /* L4_LS 110 MHz */
352 alwon_cm: alwon_cm@1400 {
/OK3568_Linux_fs/kernel/drivers/soc/samsung/
H A Dexynos5422-asv.c26 * contains frequency value in MHz and subsequent columns contain the CPU
52 { 1400, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500,
94 { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,
136 { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,
172 { 1400, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
236 { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
266 { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,

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