1*4882a593Smuzhiyun#PBL preamble and RCW header for T1024RDB 2*4882a593Smuzhiyunaa55aa55 010e0100 3*4882a593Smuzhiyun#SerDes Protocol: 0x95 4*4882a593Smuzhiyun#Core/DDR: 1400Mhz/1600MT/s with single source clock 5*4882a593Smuzhiyun0810000c 00000000 00000000 00000000 6*4882a593Smuzhiyun4a800003 80000012 6c027000 21000000 7*4882a593Smuzhiyun00000000 00000000 00000000 00030810 8*4882a593Smuzhiyun00000000 0b005a08 00000000 00000006 9