1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * K2E: Clock management APIs 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2012-2014 5*4882a593Smuzhiyun * Texas Instruments Incorporated, <www.ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_CLOCK_K2E_H 11*4882a593Smuzhiyun #define __ASM_ARCH_CLOCK_K2E_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PLLSET_CMD_LIST "<pa|ddr3>" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define KS2_CLK1_6 sys_clk0_6_clk 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CORE_PLL_800 {CORE_PLL, 16, 1, 2} 18*4882a593Smuzhiyun #define CORE_PLL_850 {CORE_PLL, 17, 1, 2} 19*4882a593Smuzhiyun #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} 20*4882a593Smuzhiyun #define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} 21*4882a593Smuzhiyun #define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} 22*4882a593Smuzhiyun #define CORE_PLL_1250 {CORE_PLL, 25, 1, 2} 23*4882a593Smuzhiyun #define CORE_PLL_1350 {CORE_PLL, 27, 1, 2} 24*4882a593Smuzhiyun #define CORE_PLL_1400 {CORE_PLL, 28, 1, 2} 25*4882a593Smuzhiyun #define CORE_PLL_1500 {CORE_PLL, 30, 1, 2} 26*4882a593Smuzhiyun #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} 27*4882a593Smuzhiyun #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} 28*4882a593Smuzhiyun #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} 29*4882a593Smuzhiyun #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */ 32*4882a593Smuzhiyun #define DEV_SUPPORTED_SPEEDS 0xFFF 33*4882a593Smuzhiyun #define ARM_SUPPORTED_SPEEDS 0 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36