1*4882a593Smuzhiyun# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz 2*4882a593Smuzhiyun# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun# PBL preamble and RCW header for T1024QDS 5*4882a593Smuzhiyunaa55aa55 010e0100 6*4882a593Smuzhiyun# Serdes protocol 0x6F 7*4882a593Smuzhiyun0810000e 00000000 00000000 00000000 8*4882a593Smuzhiyun37800001 00000012 58104000 21000000 9*4882a593Smuzhiyun00000000 00000000 00000000 00030810 10*4882a593Smuzhiyun00000000 036c5a00 00000000 00000006 11