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/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
81 # Scan Frequency 50.900 kHz 100.00 Hz
94 mode "640x480-100"
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/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dpowernow-k6.c26 static unsigned int busfreq; /* FSB, in 10 kHz */
36 MODULE_PARM_DESC(bus_frequency, "Bus frequency in kHz");
47 {0, 20, /* 100 -> 2.0x */ 0},
58 { 350000, 35 }, // 100 * 3.5
59 { 400000, 40 }, // 100 * 4
60 { 450000, 45 }, // 100 * 4.5
62 { 500000, 50 }, // 100 * 5
65 { 550000, 55 }, // 100 * 5.5
68 { 600000, 60 }, // 100 * 6
157 unsigned khz; in powernow_k6_cpu_init() local
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H A Dlongrun.c21 * longrun_{low,high}_freq is needed for the conversion of cpufreq kHz
56 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
58 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
81 pctg_lo = pctg_hi = 100; in longrun_set_policy()
84 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
86 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
89 if (pctg_hi > 100) in longrun_set_policy()
90 pctg_hi = 100; in longrun_set_policy()
183 *low_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
188 *high_freq = msr_lo * 1000; /* to kHz */ in longrun_determine_freqs()
[all …]
H A Dgx-suspmod.c89 #define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
132 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
232 /* if this relation is closer to khz, use this. If it's equal, in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
247 * set cpu speed in khz.
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
259 new_khz = gx_validate_speed(khz, &gx_params->on_duration, in gx_set_cpuspeed()
268 /* if new khz == 100% of CPU speed, it is special case */ in gx_set_cpuspeed()
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/OK3568_Linux_fs/kernel/drivers/video/fbdev/core/
H A Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
71 /* 640x480 @ 85 Hz, 43.27 kHz hsync */
75 /* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
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/OK3568_Linux_fs/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c21 #define MAX_FVCO 500000 /* KHz */
22 #define MAX_FSYS 80000 /* KHz */
23 #define MIN_FSYS 58333 /* KHz */
26 #define FREF 20000 /* KHz */
38 #define FREF 16000 /* KHz */
132 * fref PLL reference clock frequency in KHz
133 * fsys Desired PLL output frequency in KHz
174 * Multiplying by 100 when calculating the temp value, in clock_pll()
175 * and then dividing by 100 to calculate the mfd allows in clock_pll()
179 temp = (100 * fsys) / fref; in clock_pll()
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/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Ddt2811.c75 #define DT2811_OSC_BASE 1666 /* 600 kHz = 1666.6667ns */
81 * 0 1 600 kHz 0 1
82 * 1 10 60 kHz 1 10
83 * 2 2 300 kHz 2 100
84 * 3 3 200 kHz 3 1000
85 * 4 4 150 kHz 4 10000
86 * 5 5 120 kHz 5 100000
87 * 6 6 100 kHz 6 1000000
88 * 7 12 50 kHz 7 10000000
95 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h128 uint32_t pixel_clk; /* in KHz */
160 uint32_t crystal_frequency; /* in KHz */
161 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
162 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
163 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
164 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
172 uint32_t default_display_engine_pll_frequency; /* in KHz */
173 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
174 uint32_t smu_gpu_pll_output_freq; /* in KHz */
177 uint32_t default_memory_clk; /* in KHz */
[all …]
/OK3568_Linux_fs/kernel/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/OK3568_Linux_fs/kernel/drivers/devfreq/
H A Dtegra30-devfreq.c73 #define KHZ 1000 macro
75 #define KHZ_MAX (ULONG_MAX / KHZ)
99 * Threshold of activity (cycles translated to kHz) below which the
130 .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
137 * Frequencies are in kHz.
217 do_div(val, 100); in do_percent()
229 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
323 avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold; in actmon_device_target_freq()
387 tegra->cur_freq = data->new_rate / KHZ; in tegra_actmon_clk_notify_cb()
542 tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ; in tegra_actmon_resume()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/i2c/
H A Di2c-ocores.txt21 Defaults to 100 KHz when the property is not specified
33 frequency is fixed at 100 KHz.
65 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
H A Di2c-exynos5.txt4 at various speeds ranging from 100khz to 3.4Mhz.
31 at 100khz.
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-gru.dts103 // ...with no speed, it should just use 100kHz
125 // ...with no speed, it should just use 100kHz
135 // ...with no speed, it should just use 100kHz
/OK3568_Linux_fs/buildroot/dl/sox/git/scripts/
H A Dtesttones.sh97 freqs="100 1k 10k"
125 while [ $note -le 67 ]; do # 5 and a bit octaves above middle A ~= 20kHz
141 for freq in 20 50 100 200 500 1k 2k 5k 10k 20k; do
175 next_file 9kHz+10kHz
184 for freq in 100 1k 5k; do
209 synth squ amod 0 100 sine amod 8.333333333333333333 0 75 \
217 echo; echo "1kHz tone offset with 1Hz:"
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h79 #define KHz 1000 macro
91 #define PCLK_DBG_HZ (100*MHz)
95 #define PERIHP_PCLK_HZ (37500 * KHz)
98 #define PERILP0_HCLK_HZ (100 * MHz)
101 #define PERILP1_HCLK_HZ (100 * MHz)
/OK3568_Linux_fs/kernel/drivers/nvmem/
H A Dlpc18xx_eeprom.c38 /* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
109 /* Wait 100 us while the EEPROM wakes up */ in lpc18xx_eeprom_gather_write()
110 usleep_range(100, 200); in lpc18xx_eeprom_gather_write()
137 /* Wait 100 us while the EEPROM wakes up */ in lpc18xx_eeprom_read()
138 usleep_range(100, 200); in lpc18xx_eeprom_read()
/OK3568_Linux_fs/kernel/Documentation/hwmon/
H A Dlm85.rst153 driven by a 22.5 kHz clock. This is a global mode, not per-PWM output,
154 which means that setting any PWM frequency above 11.3 kHz will switch
155 all 3 PWM outputs to a 22.5 kHz frequency. Conversely, setting any PWM
156 frequency below 11.3 kHz will switch all 3 PWM outputs to a frequency
157 between 10 and 100 Hz, which can then be tuned separately.
179 The LM96000 supports additional high frequency PWM modes (22.5 kHz, 24 kHz,
180 25.7 kHz, 27.7 kHz and 30 kHz), which can be configured on a per-PWM basis.
266 -1 PWM always 100% (full on)
/OK3568_Linux_fs/kernel/drivers/iio/humidity/
H A Ddht11.c53 * 34uS > timeres > 30uS ... no problem (30kHz and 32kHz clocks)
57 * Luckily clocks in the 33-44kHz range are quite uncommon, so we can
60 * 40kHz, where this driver is most unreliable, there are two options.
152 if (hum_int < 4) { /* DHT22: 100000 = (3*256+232)*100 */ in dht11_decode()
154 ((temp_int & 0x80) ? -100 : 100); in dht11_decode()
155 dht11->humidity = ((hum_int << 8) + hum_dec) * 100; in dht11_decode()
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dmax9860.c126 static const DECLARE_TLV_DB_SCALE(dva_tlv, -9100, 100, 1);
128 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
132 static const DECLARE_TLV_DB_SCALE(pgam_tlv, 0, 100, 0);
134 static const DECLARE_TLV_DB_SCALE(agcth_tlv, -1800, 100, 0);
137 "AGC Disabled", "50ms", "100ms", "400ms"
167 "Elliptical HP 217Hz notch (16kHz)",
168 "Butterworth HP 500Hz (16kHz)",
169 "Elliptical HP 217Hz notch (8kHz)",
170 "Butterworth HP 500Hz (8kHz)",
171 "Butterworth HP 200Hz (48kHz)"
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H A Dmax98373.c88 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
91 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
95 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
98 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
105 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
106 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
109 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
166 "333kHz", "192kHz", "64kHz", "48kHz"
H A Dwm8983.c131 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
132 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
133 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
139 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
169 "650Hz", "850Hz", "1.1kHz", "1.4kHz"
174 "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
179 "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
200 "100%"
856 /* VMID at 100k */ in wm8983_set_bias_level()
878 /* VMID at 100k */ in wm8983_set_bias_level()
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/OK3568_Linux_fs/kernel/drivers/media/radio/si470x/
H A Dradio-si470x-common.c108 /* Spacing (kHz) */
109 /* 0: 200 kHz (USA, Australia) */
110 /* 1: 100 kHz (Europe, Japan) */
111 /* 2: 50 kHz */
114 MODULE_PARM_DESC(space, "Spacing: 0=200kHz 1=100kHz *2=50kHz*");
241 /* Spacing (kHz) */ in si470x_get_step()
243 /* 0: 200 kHz (USA, Australia) */ in si470x_get_step()
246 /* 1: 100 kHz (Europe, Japan) */ in si470x_get_step()
248 return 100 * 16; in si470x_get_step()
249 /* 2: 50 kHz */ in si470x_get_step()
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/
H A Dhalbb_cfo_trk.h31 #define CFO_TRK_TH_4 30 /* @kHz disable CFO_Track threshold*/
32 #define CFO_TRK_TH_3 20 /* @kHz disable CFO_Track threshold*/
33 #define CFO_TRK_TH_2 10 /* @kHz disable CFO_Track threshold*/
34 #define CFO_TRK_TH_1 0 /* @kHz disable CFO_Track threshold*/
35 #define CFO_TRK_ENABLE_TH 3 /* @kHz enable CFO_Track threshold*/
36 #define CFO_TRK_STOP_TH 3 /* @kHz disable CFO_Track threshold*/
38 #define CFO_SW_COMP_FINE_TUNE 5 /* @kHz expected CFO Comp. per Xcap ofst*/ /*0.8ppm~1ppm per Xcap …
39 #define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
41 #define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
46 #define STA_CFO_TOLERANCE_2G 30 /* kHz */
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/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/
H A Dhalbb_cfo_trk.h31 #define CFO_TRK_TH_4 30 /* @kHz disable CFO_Track threshold*/
32 #define CFO_TRK_TH_3 20 /* @kHz disable CFO_Track threshold*/
33 #define CFO_TRK_TH_2 10 /* @kHz disable CFO_Track threshold*/
34 #define CFO_TRK_TH_1 0 /* @kHz disable CFO_Track threshold*/
35 #define CFO_TRK_ENABLE_TH 3 /* @kHz enable CFO_Track threshold*/
36 #define CFO_TRK_STOP_TH 3 /* @kHz disable CFO_Track threshold*/
38 #define CFO_SW_COMP_FINE_TUNE 5 /* @kHz expected CFO Comp. per Xcap ofst*/ /*0.8ppm~1ppm per Xcap …
39 #define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
41 #define DIGI_CFO_COMP_LIMIT 5 /* @kHz enable digital CFO comp threshold*/
46 #define STA_CFO_TOLERANCE_2G 30 /* kHz */
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsun5i-reference-design-tablet.dtsi55 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
87 * The gsl1680 is rated at 400KHz and it will not work reliable at
88 * 100KHz, this has been confirmed on multiple different q8 tablets.
89 * All other devices on this bus are also rated for 400KHz.

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