1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Cyrix MediaGX and NatSemi Geode Suspend Modulation
4*4882a593Smuzhiyun * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
5*4882a593Smuzhiyun * (C) 2002 Hiroshi Miura <miura@da-cha.org>
6*4882a593Smuzhiyun * All Rights Reserved
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * The author(s) of this software shall not be held liable for damages
9*4882a593Smuzhiyun * of any nature resulting due to the use of this software. This
10*4882a593Smuzhiyun * software is provided AS-IS with no warranties.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Theoretical note:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * (see Geode(tm) CS5530 manual (rev.4.1) page.56)
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * CPU frequency control on NatSemi Geode GX1/GXLV processor and CS55x0
17*4882a593Smuzhiyun * are based on Suspend Modulation.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * Suspend Modulation works by asserting and de-asserting the SUSP# pin
20*4882a593Smuzhiyun * to CPU(GX1/GXLV) for configurable durations. When asserting SUSP#
21*4882a593Smuzhiyun * the CPU enters an idle state. GX1 stops its core clock when SUSP# is
22*4882a593Smuzhiyun * asserted then power consumption is reduced.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * Suspend Modulation's OFF/ON duration are configurable
25*4882a593Smuzhiyun * with 'Suspend Modulation OFF Count Register'
26*4882a593Smuzhiyun * and 'Suspend Modulation ON Count Register'.
27*4882a593Smuzhiyun * These registers are 8bit counters that represent the number of
28*4882a593Smuzhiyun * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
29*4882a593Smuzhiyun * to the processor.
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * These counters define a ratio which is the effective frequency
32*4882a593Smuzhiyun * of operation of the system.
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * OFF Count
35*4882a593Smuzhiyun * F_eff = Fgx * ----------------------
36*4882a593Smuzhiyun * OFF Count + ON Count
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * 0 <= On Count, Off Count <= 255
39*4882a593Smuzhiyun *
40*4882a593Smuzhiyun * From these limits, we can get register values
41*4882a593Smuzhiyun *
42*4882a593Smuzhiyun * off_duration + on_duration <= MAX_DURATION
43*4882a593Smuzhiyun * on_duration = off_duration * (stock_freq - freq) / freq
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * off_duration = (freq * DURATION) / stock_freq
46*4882a593Smuzhiyun * on_duration = DURATION - off_duration
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun *---------------------------------------------------------------------------
49*4882a593Smuzhiyun *
50*4882a593Smuzhiyun * ChangeLog:
51*4882a593Smuzhiyun * Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org>
52*4882a593Smuzhiyun * - fix on/off register mistake
53*4882a593Smuzhiyun * - fix cpu_khz calc when it stops cpu modulation.
54*4882a593Smuzhiyun *
55*4882a593Smuzhiyun * Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org>
56*4882a593Smuzhiyun * - rewrite for Cyrix MediaGX Cx5510/5520 and
57*4882a593Smuzhiyun * NatSemi Geode Cs5530(A).
58*4882a593Smuzhiyun *
59*4882a593Smuzhiyun * Jul. ??, 2002 Zwane Mwaikambo <zwane@commfireservices.com>
60*4882a593Smuzhiyun * - cs5530_mod patch for 2.4.19-rc1.
61*4882a593Smuzhiyun *
62*4882a593Smuzhiyun *---------------------------------------------------------------------------
63*4882a593Smuzhiyun *
64*4882a593Smuzhiyun * Todo
65*4882a593Smuzhiyun * Test on machines with 5510, 5530, 5530A
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /************************************************************************
69*4882a593Smuzhiyun * Suspend Modulation - Definitions *
70*4882a593Smuzhiyun ************************************************************************/
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #include <linux/kernel.h>
73*4882a593Smuzhiyun #include <linux/module.h>
74*4882a593Smuzhiyun #include <linux/init.h>
75*4882a593Smuzhiyun #include <linux/smp.h>
76*4882a593Smuzhiyun #include <linux/cpufreq.h>
77*4882a593Smuzhiyun #include <linux/pci.h>
78*4882a593Smuzhiyun #include <linux/errno.h>
79*4882a593Smuzhiyun #include <linux/slab.h>
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #include <asm/cpu_device_id.h>
82*4882a593Smuzhiyun #include <asm/processor-cyrix.h>
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* PCI config registers, all at F0 */
85*4882a593Smuzhiyun #define PCI_PMER1 0x80 /* power management enable register 1 */
86*4882a593Smuzhiyun #define PCI_PMER2 0x81 /* power management enable register 2 */
87*4882a593Smuzhiyun #define PCI_PMER3 0x82 /* power management enable register 3 */
88*4882a593Smuzhiyun #define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */
89*4882a593Smuzhiyun #define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */
90*4882a593Smuzhiyun #define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
91*4882a593Smuzhiyun #define PCI_MODON 0x95 /* suspend modulation ON counter register */
92*4882a593Smuzhiyun #define PCI_SUSCFG 0x96 /* suspend configuration register */
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* PMER1 bits */
95*4882a593Smuzhiyun #define GPM (1<<0) /* global power management */
96*4882a593Smuzhiyun #define GIT (1<<1) /* globally enable PM device idle timers */
97*4882a593Smuzhiyun #define GTR (1<<2) /* globally enable IO traps */
98*4882a593Smuzhiyun #define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */
99*4882a593Smuzhiyun #define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* SUSCFG bits */
102*4882a593Smuzhiyun #define SUSMOD (1<<0) /* enable/disable suspend modulation */
103*4882a593Smuzhiyun /* the below is supported only with cs5530 (after rev.1.2)/cs5530A */
104*4882a593Smuzhiyun #define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */
105*4882a593Smuzhiyun /* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */
106*4882a593Smuzhiyun #define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */
107*4882a593Smuzhiyun /* the below is supported only with cs5530A */
108*4882a593Smuzhiyun #define PWRSVE_ISA (1<<3) /* stop ISA clock */
109*4882a593Smuzhiyun #define PWRSVE (1<<4) /* active idle */
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun struct gxfreq_params {
112*4882a593Smuzhiyun u8 on_duration;
113*4882a593Smuzhiyun u8 off_duration;
114*4882a593Smuzhiyun u8 pci_suscfg;
115*4882a593Smuzhiyun u8 pci_pmer1;
116*4882a593Smuzhiyun u8 pci_pmer2;
117*4882a593Smuzhiyun struct pci_dev *cs55x0;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static struct gxfreq_params *gx_params;
121*4882a593Smuzhiyun static int stock_freq;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* PCI bus clock - defaults to 30.000 if cpu_khz is not available */
124*4882a593Smuzhiyun static int pci_busclk;
125*4882a593Smuzhiyun module_param(pci_busclk, int, 0444);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* maximum duration for which the cpu may be suspended
128*4882a593Smuzhiyun * (32us * MAX_DURATION). If no parameter is given, this defaults
129*4882a593Smuzhiyun * to 255.
130*4882a593Smuzhiyun * Note that this leads to a maximum of 8 ms(!) where the CPU clock
131*4882a593Smuzhiyun * is suspended -- processing power is just 0.39% of what it used to be,
132*4882a593Smuzhiyun * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
133*4882a593Smuzhiyun static int max_duration = 255;
134*4882a593Smuzhiyun module_param(max_duration, int, 0444);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /* For the default policy, we want at least some processing power
137*4882a593Smuzhiyun * - let's say 5%. (min = maxfreq / POLICY_MIN_DIV)
138*4882a593Smuzhiyun */
139*4882a593Smuzhiyun #define POLICY_MIN_DIV 20
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /**
143*4882a593Smuzhiyun * we can detect a core multiplier from dir0_lsb
144*4882a593Smuzhiyun * from GX1 datasheet p.56,
145*4882a593Smuzhiyun * MULT[3:0]:
146*4882a593Smuzhiyun * 0000 = SYSCLK multiplied by 4 (test only)
147*4882a593Smuzhiyun * 0001 = SYSCLK multiplied by 10
148*4882a593Smuzhiyun * 0010 = SYSCLK multiplied by 4
149*4882a593Smuzhiyun * 0011 = SYSCLK multiplied by 6
150*4882a593Smuzhiyun * 0100 = SYSCLK multiplied by 9
151*4882a593Smuzhiyun * 0101 = SYSCLK multiplied by 5
152*4882a593Smuzhiyun * 0110 = SYSCLK multiplied by 7
153*4882a593Smuzhiyun * 0111 = SYSCLK multiplied by 8
154*4882a593Smuzhiyun * of 33.3MHz
155*4882a593Smuzhiyun **/
156*4882a593Smuzhiyun static int gx_freq_mult[16] = {
157*4882a593Smuzhiyun 4, 10, 4, 6, 9, 5, 7, 8,
158*4882a593Smuzhiyun 0, 0, 0, 0, 0, 0, 0, 0
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /****************************************************************
163*4882a593Smuzhiyun * Low Level chipset interface *
164*4882a593Smuzhiyun ****************************************************************/
165*4882a593Smuzhiyun static struct pci_device_id gx_chipset_tbl[] __initdata = {
166*4882a593Smuzhiyun { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY), },
167*4882a593Smuzhiyun { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
168*4882a593Smuzhiyun { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
169*4882a593Smuzhiyun { 0, },
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, gx_chipset_tbl);
172*4882a593Smuzhiyun
gx_write_byte(int reg,int value)173*4882a593Smuzhiyun static void gx_write_byte(int reg, int value)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun pci_write_config_byte(gx_params->cs55x0, reg, value);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /**
179*4882a593Smuzhiyun * gx_detect_chipset:
180*4882a593Smuzhiyun *
181*4882a593Smuzhiyun **/
gx_detect_chipset(void)182*4882a593Smuzhiyun static struct pci_dev * __init gx_detect_chipset(void)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct pci_dev *gx_pci = NULL;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* detect which companion chip is used */
187*4882a593Smuzhiyun for_each_pci_dev(gx_pci) {
188*4882a593Smuzhiyun if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL)
189*4882a593Smuzhiyun return gx_pci;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun pr_debug("error: no supported chipset found!\n");
193*4882a593Smuzhiyun return NULL;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /**
197*4882a593Smuzhiyun * gx_get_cpuspeed:
198*4882a593Smuzhiyun *
199*4882a593Smuzhiyun * Finds out at which efficient frequency the Cyrix MediaGX/NatSemi
200*4882a593Smuzhiyun * Geode CPU runs.
201*4882a593Smuzhiyun */
gx_get_cpuspeed(unsigned int cpu)202*4882a593Smuzhiyun static unsigned int gx_get_cpuspeed(unsigned int cpu)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun if ((gx_params->pci_suscfg & SUSMOD) == 0)
205*4882a593Smuzhiyun return stock_freq;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun return (stock_freq * gx_params->off_duration)
208*4882a593Smuzhiyun / (gx_params->on_duration + gx_params->off_duration);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /**
212*4882a593Smuzhiyun * gx_validate_speed:
213*4882a593Smuzhiyun * determine current cpu speed
214*4882a593Smuzhiyun *
215*4882a593Smuzhiyun **/
216*4882a593Smuzhiyun
gx_validate_speed(unsigned int khz,u8 * on_duration,u8 * off_duration)217*4882a593Smuzhiyun static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration,
218*4882a593Smuzhiyun u8 *off_duration)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun unsigned int i;
221*4882a593Smuzhiyun u8 tmp_on, tmp_off;
222*4882a593Smuzhiyun int old_tmp_freq = stock_freq;
223*4882a593Smuzhiyun int tmp_freq;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun *off_duration = 1;
226*4882a593Smuzhiyun *on_duration = 0;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun for (i = max_duration; i > 0; i--) {
229*4882a593Smuzhiyun tmp_off = ((khz * i) / stock_freq) & 0xff;
230*4882a593Smuzhiyun tmp_on = i - tmp_off;
231*4882a593Smuzhiyun tmp_freq = (stock_freq * tmp_off) / i;
232*4882a593Smuzhiyun /* if this relation is closer to khz, use this. If it's equal,
233*4882a593Smuzhiyun * prefer it, too - lower latency */
234*4882a593Smuzhiyun if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) {
235*4882a593Smuzhiyun *on_duration = tmp_on;
236*4882a593Smuzhiyun *off_duration = tmp_off;
237*4882a593Smuzhiyun old_tmp_freq = tmp_freq;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun return old_tmp_freq;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /**
246*4882a593Smuzhiyun * gx_set_cpuspeed:
247*4882a593Smuzhiyun * set cpu speed in khz.
248*4882a593Smuzhiyun **/
249*4882a593Smuzhiyun
gx_set_cpuspeed(struct cpufreq_policy * policy,unsigned int khz)250*4882a593Smuzhiyun static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun u8 suscfg, pmer1;
253*4882a593Smuzhiyun unsigned int new_khz;
254*4882a593Smuzhiyun unsigned long flags;
255*4882a593Smuzhiyun struct cpufreq_freqs freqs;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun freqs.old = gx_get_cpuspeed(0);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun new_khz = gx_validate_speed(khz, &gx_params->on_duration,
260*4882a593Smuzhiyun &gx_params->off_duration);
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun freqs.new = new_khz;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun cpufreq_freq_transition_begin(policy, &freqs);
265*4882a593Smuzhiyun local_irq_save(flags);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (new_khz != stock_freq) {
268*4882a593Smuzhiyun /* if new khz == 100% of CPU speed, it is special case */
269*4882a593Smuzhiyun switch (gx_params->cs55x0->device) {
270*4882a593Smuzhiyun case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
271*4882a593Smuzhiyun pmer1 = gx_params->pci_pmer1 | IRQ_SPDUP | VID_SPDUP;
272*4882a593Smuzhiyun /* FIXME: need to test other values -- Zwane,Miura */
273*4882a593Smuzhiyun /* typical 2 to 4ms */
274*4882a593Smuzhiyun gx_write_byte(PCI_IRQTC, 4);
275*4882a593Smuzhiyun /* typical 50 to 100ms */
276*4882a593Smuzhiyun gx_write_byte(PCI_VIDTC, 100);
277*4882a593Smuzhiyun gx_write_byte(PCI_PMER1, pmer1);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (gx_params->cs55x0->revision < 0x10) {
280*4882a593Smuzhiyun /* CS5530(rev 1.2, 1.3) */
281*4882a593Smuzhiyun suscfg = gx_params->pci_suscfg|SUSMOD;
282*4882a593Smuzhiyun } else {
283*4882a593Smuzhiyun /* CS5530A,B.. */
284*4882a593Smuzhiyun suscfg = gx_params->pci_suscfg|SUSMOD|PWRSVE;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun break;
287*4882a593Smuzhiyun case PCI_DEVICE_ID_CYRIX_5520:
288*4882a593Smuzhiyun case PCI_DEVICE_ID_CYRIX_5510:
289*4882a593Smuzhiyun suscfg = gx_params->pci_suscfg | SUSMOD;
290*4882a593Smuzhiyun break;
291*4882a593Smuzhiyun default:
292*4882a593Smuzhiyun local_irq_restore(flags);
293*4882a593Smuzhiyun pr_debug("fatal: try to set unknown chipset.\n");
294*4882a593Smuzhiyun return;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun } else {
297*4882a593Smuzhiyun suscfg = gx_params->pci_suscfg & ~(SUSMOD);
298*4882a593Smuzhiyun gx_params->off_duration = 0;
299*4882a593Smuzhiyun gx_params->on_duration = 0;
300*4882a593Smuzhiyun pr_debug("suspend modulation disabled: cpu runs 100%% speed.\n");
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun gx_write_byte(PCI_MODOFF, gx_params->off_duration);
304*4882a593Smuzhiyun gx_write_byte(PCI_MODON, gx_params->on_duration);
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun gx_write_byte(PCI_SUSCFG, suscfg);
307*4882a593Smuzhiyun pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun local_irq_restore(flags);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun gx_params->pci_suscfg = suscfg;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun cpufreq_freq_transition_end(policy, &freqs, 0);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun pr_debug("suspend modulation w/ duration of ON:%d us, OFF:%d us\n",
316*4882a593Smuzhiyun gx_params->on_duration * 32, gx_params->off_duration * 32);
317*4882a593Smuzhiyun pr_debug("suspend modulation w/ clock speed: %d kHz.\n", freqs.new);
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun /****************************************************************
321*4882a593Smuzhiyun * High level functions *
322*4882a593Smuzhiyun ****************************************************************/
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /*
325*4882a593Smuzhiyun * cpufreq_gx_verify: test if frequency range is valid
326*4882a593Smuzhiyun *
327*4882a593Smuzhiyun * This function checks if a given frequency range in kHz is valid
328*4882a593Smuzhiyun * for the hardware supported by the driver.
329*4882a593Smuzhiyun */
330*4882a593Smuzhiyun
cpufreq_gx_verify(struct cpufreq_policy_data * policy)331*4882a593Smuzhiyun static int cpufreq_gx_verify(struct cpufreq_policy_data *policy)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun unsigned int tmp_freq = 0;
334*4882a593Smuzhiyun u8 tmp1, tmp2;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun if (!stock_freq || !policy)
337*4882a593Smuzhiyun return -EINVAL;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun policy->cpu = 0;
340*4882a593Smuzhiyun cpufreq_verify_within_limits(policy, (stock_freq / max_duration),
341*4882a593Smuzhiyun stock_freq);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun /* it needs to be assured that at least one supported frequency is
344*4882a593Smuzhiyun * within policy->min and policy->max. If it is not, policy->max
345*4882a593Smuzhiyun * needs to be increased until one frequency is supported.
346*4882a593Smuzhiyun * policy->min may not be decreased, though. This way we guarantee a
347*4882a593Smuzhiyun * specific processing capacity.
348*4882a593Smuzhiyun */
349*4882a593Smuzhiyun tmp_freq = gx_validate_speed(policy->min, &tmp1, &tmp2);
350*4882a593Smuzhiyun if (tmp_freq < policy->min)
351*4882a593Smuzhiyun tmp_freq += stock_freq / max_duration;
352*4882a593Smuzhiyun policy->min = tmp_freq;
353*4882a593Smuzhiyun if (policy->min > policy->max)
354*4882a593Smuzhiyun policy->max = tmp_freq;
355*4882a593Smuzhiyun tmp_freq = gx_validate_speed(policy->max, &tmp1, &tmp2);
356*4882a593Smuzhiyun if (tmp_freq > policy->max)
357*4882a593Smuzhiyun tmp_freq -= stock_freq / max_duration;
358*4882a593Smuzhiyun policy->max = tmp_freq;
359*4882a593Smuzhiyun if (policy->max < policy->min)
360*4882a593Smuzhiyun policy->max = policy->min;
361*4882a593Smuzhiyun cpufreq_verify_within_limits(policy, (stock_freq / max_duration),
362*4882a593Smuzhiyun stock_freq);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun return 0;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /*
368*4882a593Smuzhiyun * cpufreq_gx_target:
369*4882a593Smuzhiyun *
370*4882a593Smuzhiyun */
cpufreq_gx_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)371*4882a593Smuzhiyun static int cpufreq_gx_target(struct cpufreq_policy *policy,
372*4882a593Smuzhiyun unsigned int target_freq,
373*4882a593Smuzhiyun unsigned int relation)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun u8 tmp1, tmp2;
376*4882a593Smuzhiyun unsigned int tmp_freq;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun if (!stock_freq || !policy)
379*4882a593Smuzhiyun return -EINVAL;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun policy->cpu = 0;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun tmp_freq = gx_validate_speed(target_freq, &tmp1, &tmp2);
384*4882a593Smuzhiyun while (tmp_freq < policy->min) {
385*4882a593Smuzhiyun tmp_freq += stock_freq / max_duration;
386*4882a593Smuzhiyun tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun while (tmp_freq > policy->max) {
389*4882a593Smuzhiyun tmp_freq -= stock_freq / max_duration;
390*4882a593Smuzhiyun tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2);
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun gx_set_cpuspeed(policy, tmp_freq);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun return 0;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
cpufreq_gx_cpu_init(struct cpufreq_policy * policy)398*4882a593Smuzhiyun static int cpufreq_gx_cpu_init(struct cpufreq_policy *policy)
399*4882a593Smuzhiyun {
400*4882a593Smuzhiyun unsigned int maxfreq;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun if (!policy || policy->cpu != 0)
403*4882a593Smuzhiyun return -ENODEV;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun /* determine maximum frequency */
406*4882a593Smuzhiyun if (pci_busclk)
407*4882a593Smuzhiyun maxfreq = pci_busclk * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
408*4882a593Smuzhiyun else if (cpu_khz)
409*4882a593Smuzhiyun maxfreq = cpu_khz;
410*4882a593Smuzhiyun else
411*4882a593Smuzhiyun maxfreq = 30000 * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f];
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun stock_freq = maxfreq;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun pr_debug("cpu max frequency is %d.\n", maxfreq);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* setup basic struct for cpufreq API */
418*4882a593Smuzhiyun policy->cpu = 0;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun if (max_duration < POLICY_MIN_DIV)
421*4882a593Smuzhiyun policy->min = maxfreq / max_duration;
422*4882a593Smuzhiyun else
423*4882a593Smuzhiyun policy->min = maxfreq / POLICY_MIN_DIV;
424*4882a593Smuzhiyun policy->max = maxfreq;
425*4882a593Smuzhiyun policy->cpuinfo.min_freq = maxfreq / max_duration;
426*4882a593Smuzhiyun policy->cpuinfo.max_freq = maxfreq;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun return 0;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun /*
432*4882a593Smuzhiyun * cpufreq_gx_init:
433*4882a593Smuzhiyun * MediaGX/Geode GX initialize cpufreq driver
434*4882a593Smuzhiyun */
435*4882a593Smuzhiyun static struct cpufreq_driver gx_suspmod_driver = {
436*4882a593Smuzhiyun .flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
437*4882a593Smuzhiyun .get = gx_get_cpuspeed,
438*4882a593Smuzhiyun .verify = cpufreq_gx_verify,
439*4882a593Smuzhiyun .target = cpufreq_gx_target,
440*4882a593Smuzhiyun .init = cpufreq_gx_cpu_init,
441*4882a593Smuzhiyun .name = "gx-suspmod",
442*4882a593Smuzhiyun };
443*4882a593Smuzhiyun
cpufreq_gx_init(void)444*4882a593Smuzhiyun static int __init cpufreq_gx_init(void)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun int ret;
447*4882a593Smuzhiyun struct gxfreq_params *params;
448*4882a593Smuzhiyun struct pci_dev *gx_pci;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun /* Test if we have the right hardware */
451*4882a593Smuzhiyun gx_pci = gx_detect_chipset();
452*4882a593Smuzhiyun if (gx_pci == NULL)
453*4882a593Smuzhiyun return -ENODEV;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun /* check whether module parameters are sane */
456*4882a593Smuzhiyun if (max_duration > 0xff)
457*4882a593Smuzhiyun max_duration = 0xff;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun pr_debug("geode suspend modulation available.\n");
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun params = kzalloc(sizeof(*params), GFP_KERNEL);
462*4882a593Smuzhiyun if (params == NULL)
463*4882a593Smuzhiyun return -ENOMEM;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun params->cs55x0 = gx_pci;
466*4882a593Smuzhiyun gx_params = params;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun /* keep cs55x0 configurations */
469*4882a593Smuzhiyun pci_read_config_byte(params->cs55x0, PCI_SUSCFG, &(params->pci_suscfg));
470*4882a593Smuzhiyun pci_read_config_byte(params->cs55x0, PCI_PMER1, &(params->pci_pmer1));
471*4882a593Smuzhiyun pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2));
472*4882a593Smuzhiyun pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration));
473*4882a593Smuzhiyun pci_read_config_byte(params->cs55x0, PCI_MODOFF,
474*4882a593Smuzhiyun &(params->off_duration));
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun ret = cpufreq_register_driver(&gx_suspmod_driver);
477*4882a593Smuzhiyun if (ret) {
478*4882a593Smuzhiyun kfree(params);
479*4882a593Smuzhiyun return ret; /* register error! */
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun return 0;
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
cpufreq_gx_exit(void)485*4882a593Smuzhiyun static void __exit cpufreq_gx_exit(void)
486*4882a593Smuzhiyun {
487*4882a593Smuzhiyun cpufreq_unregister_driver(&gx_suspmod_driver);
488*4882a593Smuzhiyun pci_dev_put(gx_params->cs55x0);
489*4882a593Smuzhiyun kfree(gx_params);
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun MODULE_AUTHOR("Hiroshi Miura <miura@da-cha.org>");
493*4882a593Smuzhiyun MODULE_DESCRIPTION("Cpufreq driver for Cyrix MediaGX and NatSemi Geode");
494*4882a593Smuzhiyun MODULE_LICENSE("GPL");
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun module_init(cpufreq_gx_init);
497*4882a593Smuzhiyun module_exit(cpufreq_gx_exit);
498*4882a593Smuzhiyun
499