xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/max9860.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Driver for the MAX9860 Mono Audio Voice Codec
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // https://datasheets.maximintegrated.com/en/ds/MAX9860.pdf
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // The driver does not support sidetone since the DVST register field is
8*4882a593Smuzhiyun // backwards with the mute near the maximum level instead of the minimum.
9*4882a593Smuzhiyun //
10*4882a593Smuzhiyun // Author: Peter Rosin <peda@axentia.s>
11*4882a593Smuzhiyun //         Copyright 2016 Axentia Technologies
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/clk.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun #include <linux/i2c.h>
20*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
21*4882a593Smuzhiyun #include <sound/soc.h>
22*4882a593Smuzhiyun #include <sound/soc-dapm.h>
23*4882a593Smuzhiyun #include <sound/pcm_params.h>
24*4882a593Smuzhiyun #include <sound/tlv.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include "max9860.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun struct max9860_priv {
29*4882a593Smuzhiyun 	struct regmap *regmap;
30*4882a593Smuzhiyun 	struct regulator *dvddio;
31*4882a593Smuzhiyun 	struct notifier_block dvddio_nb;
32*4882a593Smuzhiyun 	u8 psclk;
33*4882a593Smuzhiyun 	unsigned long pclk_rate;
34*4882a593Smuzhiyun 	int fmt;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
max9860_dvddio_event(struct notifier_block * nb,unsigned long event,void * data)37*4882a593Smuzhiyun static int max9860_dvddio_event(struct notifier_block *nb,
38*4882a593Smuzhiyun 				unsigned long event, void *data)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	struct max9860_priv *max9860 = container_of(nb, struct max9860_priv,
41*4882a593Smuzhiyun 						    dvddio_nb);
42*4882a593Smuzhiyun 	if (event & REGULATOR_EVENT_DISABLE) {
43*4882a593Smuzhiyun 		regcache_mark_dirty(max9860->regmap);
44*4882a593Smuzhiyun 		regcache_cache_only(max9860->regmap, true);
45*4882a593Smuzhiyun 	}
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	return 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun static const struct reg_default max9860_reg_defaults[] = {
51*4882a593Smuzhiyun 	{ MAX9860_PWRMAN,       0x00 },
52*4882a593Smuzhiyun 	{ MAX9860_INTEN,        0x00 },
53*4882a593Smuzhiyun 	{ MAX9860_SYSCLK,       0x00 },
54*4882a593Smuzhiyun 	{ MAX9860_AUDIOCLKHIGH, 0x00 },
55*4882a593Smuzhiyun 	{ MAX9860_AUDIOCLKLOW,  0x00 },
56*4882a593Smuzhiyun 	{ MAX9860_IFC1A,        0x00 },
57*4882a593Smuzhiyun 	{ MAX9860_IFC1B,        0x00 },
58*4882a593Smuzhiyun 	{ MAX9860_VOICEFLTR,    0x00 },
59*4882a593Smuzhiyun 	{ MAX9860_DACATTN,      0x00 },
60*4882a593Smuzhiyun 	{ MAX9860_ADCLEVEL,     0x00 },
61*4882a593Smuzhiyun 	{ MAX9860_DACGAIN,      0x00 },
62*4882a593Smuzhiyun 	{ MAX9860_MICGAIN,      0x00 },
63*4882a593Smuzhiyun 	{ MAX9860_MICADC,       0x00 },
64*4882a593Smuzhiyun 	{ MAX9860_NOISEGATE,    0x00 },
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
max9860_readable(struct device * dev,unsigned int reg)67*4882a593Smuzhiyun static bool max9860_readable(struct device *dev, unsigned int reg)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	switch (reg) {
70*4882a593Smuzhiyun 	case MAX9860_INTRSTATUS ... MAX9860_MICGAIN:
71*4882a593Smuzhiyun 	case MAX9860_MICADC ... MAX9860_PWRMAN:
72*4882a593Smuzhiyun 	case MAX9860_REVISION:
73*4882a593Smuzhiyun 		return true;
74*4882a593Smuzhiyun 	}
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	return false;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
max9860_writeable(struct device * dev,unsigned int reg)79*4882a593Smuzhiyun static bool max9860_writeable(struct device *dev, unsigned int reg)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	switch (reg) {
82*4882a593Smuzhiyun 	case MAX9860_INTEN ... MAX9860_MICGAIN:
83*4882a593Smuzhiyun 	case MAX9860_MICADC ... MAX9860_PWRMAN:
84*4882a593Smuzhiyun 		return true;
85*4882a593Smuzhiyun 	}
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	return false;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
max9860_volatile(struct device * dev,unsigned int reg)90*4882a593Smuzhiyun static bool max9860_volatile(struct device *dev, unsigned int reg)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	switch (reg) {
93*4882a593Smuzhiyun 	case MAX9860_INTRSTATUS:
94*4882a593Smuzhiyun 	case MAX9860_MICREADBACK:
95*4882a593Smuzhiyun 		return true;
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	return false;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
max9860_precious(struct device * dev,unsigned int reg)101*4882a593Smuzhiyun static bool max9860_precious(struct device *dev, unsigned int reg)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	switch (reg) {
104*4882a593Smuzhiyun 	case MAX9860_INTRSTATUS:
105*4882a593Smuzhiyun 		return true;
106*4882a593Smuzhiyun 	}
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	return false;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun static const struct regmap_config max9860_regmap = {
112*4882a593Smuzhiyun 	.reg_bits = 8,
113*4882a593Smuzhiyun 	.val_bits = 8,
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	.readable_reg = max9860_readable,
116*4882a593Smuzhiyun 	.writeable_reg = max9860_writeable,
117*4882a593Smuzhiyun 	.volatile_reg = max9860_volatile,
118*4882a593Smuzhiyun 	.precious_reg = max9860_precious,
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	.max_register = MAX9860_MAX_REGISTER,
121*4882a593Smuzhiyun 	.reg_defaults = max9860_reg_defaults,
122*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(max9860_reg_defaults),
123*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(dva_tlv, -9100, 100, 1);
127*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(dvg_tlv, 0, 600, 0);
128*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
129*4882a593Smuzhiyun static const DECLARE_TLV_DB_RANGE(pam_tlv,
130*4882a593Smuzhiyun 	0, MAX9860_PAM_MAX - 1,             TLV_DB_SCALE_ITEM(-2000, 2000, 1),
131*4882a593Smuzhiyun 	MAX9860_PAM_MAX, MAX9860_PAM_MAX,   TLV_DB_SCALE_ITEM(3000, 0, 0));
132*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(pgam_tlv, 0, 100, 0);
133*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(anth_tlv, -7600, 400, 1);
134*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(agcth_tlv, -1800, 100, 0);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun static const char * const agchld_text[] = {
137*4882a593Smuzhiyun 	"AGC Disabled", "50ms", "100ms", "400ms"
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(agchld_enum, MAX9860_MICADC,
141*4882a593Smuzhiyun 			    MAX9860_AGCHLD_SHIFT, agchld_text);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static const char * const agcsrc_text[] = {
144*4882a593Smuzhiyun 	"Left ADC", "Left/Right ADC"
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(agcsrc_enum, MAX9860_MICADC,
148*4882a593Smuzhiyun 			    MAX9860_AGCSRC_SHIFT, agcsrc_text);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun static const char * const agcatk_text[] = {
151*4882a593Smuzhiyun 	"3ms", "12ms", "50ms", "200ms"
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(agcatk_enum, MAX9860_MICADC,
155*4882a593Smuzhiyun 			    MAX9860_AGCATK_SHIFT, agcatk_text);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun static const char * const agcrls_text[] = {
158*4882a593Smuzhiyun 	"78ms", "156ms", "312ms", "625ms",
159*4882a593Smuzhiyun 	"1.25s", "2.5s", "5s", "10s"
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(agcrls_enum, MAX9860_MICADC,
163*4882a593Smuzhiyun 			    MAX9860_AGCRLS_SHIFT, agcrls_text);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun static const char * const filter_text[] = {
166*4882a593Smuzhiyun 	"Disabled",
167*4882a593Smuzhiyun 	"Elliptical HP 217Hz notch (16kHz)",
168*4882a593Smuzhiyun 	"Butterworth HP 500Hz (16kHz)",
169*4882a593Smuzhiyun 	"Elliptical HP 217Hz notch (8kHz)",
170*4882a593Smuzhiyun 	"Butterworth HP 500Hz (8kHz)",
171*4882a593Smuzhiyun 	"Butterworth HP 200Hz (48kHz)"
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(avflt_enum, MAX9860_VOICEFLTR,
175*4882a593Smuzhiyun 			    MAX9860_AVFLT_SHIFT, filter_text);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(dvflt_enum, MAX9860_VOICEFLTR,
178*4882a593Smuzhiyun 			    MAX9860_DVFLT_SHIFT, filter_text);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun static const struct snd_kcontrol_new max9860_controls[] = {
181*4882a593Smuzhiyun SOC_SINGLE_TLV("Master Playback Volume", MAX9860_DACATTN,
182*4882a593Smuzhiyun 	       MAX9860_DVA_SHIFT, MAX9860_DVA_MUTE, 1, dva_tlv),
183*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC Gain Volume", MAX9860_DACGAIN,
184*4882a593Smuzhiyun 	       MAX9860_DVG_SHIFT, MAX9860_DVG_MAX, 0, dvg_tlv),
185*4882a593Smuzhiyun SOC_DOUBLE_TLV("Line Capture Volume", MAX9860_ADCLEVEL,
186*4882a593Smuzhiyun 	       MAX9860_ADCLL_SHIFT, MAX9860_ADCRL_SHIFT, MAX9860_ADCxL_MIN, 1,
187*4882a593Smuzhiyun 	       adc_tlv),
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun SOC_ENUM("AGC Hold Time", agchld_enum),
190*4882a593Smuzhiyun SOC_ENUM("AGC/Noise Gate Source", agcsrc_enum),
191*4882a593Smuzhiyun SOC_ENUM("AGC Attack Time", agcatk_enum),
192*4882a593Smuzhiyun SOC_ENUM("AGC Release Time", agcrls_enum),
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun SOC_SINGLE_TLV("Noise Gate Threshold Volume", MAX9860_NOISEGATE,
195*4882a593Smuzhiyun 	       MAX9860_ANTH_SHIFT, MAX9860_ANTH_MAX, 0, anth_tlv),
196*4882a593Smuzhiyun SOC_SINGLE_TLV("AGC Signal Threshold Volume", MAX9860_NOISEGATE,
197*4882a593Smuzhiyun 	       MAX9860_AGCTH_SHIFT, MAX9860_AGCTH_MIN, 1, agcth_tlv),
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun SOC_SINGLE_TLV("Mic PGA Volume", MAX9860_MICGAIN,
200*4882a593Smuzhiyun 	       MAX9860_PGAM_SHIFT, MAX9860_PGAM_MIN, 1, pgam_tlv),
201*4882a593Smuzhiyun SOC_SINGLE_TLV("Mic Preamp Volume", MAX9860_MICGAIN,
202*4882a593Smuzhiyun 	       MAX9860_PAM_SHIFT, MAX9860_PAM_MAX, 0, pam_tlv),
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun SOC_ENUM("ADC Filter", avflt_enum),
205*4882a593Smuzhiyun SOC_ENUM("DAC Filter", dvflt_enum),
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static const struct snd_soc_dapm_widget max9860_dapm_widgets[] = {
209*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICL"),
210*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICR"),
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADCL", NULL, MAX9860_PWRMAN, MAX9860_ADCLEN_SHIFT, 0),
213*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADCR", NULL, MAX9860_PWRMAN, MAX9860_ADCREN_SHIFT, 0),
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
216*4882a593Smuzhiyun SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
219*4882a593Smuzhiyun SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC", NULL, MAX9860_PWRMAN, MAX9860_DACEN_SHIFT, 0),
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("OUT"),
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Supply", SND_SOC_NOPM, 0, 0,
226*4882a593Smuzhiyun 		    NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
227*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("AVDD", 0, 0),
228*4882a593Smuzhiyun SND_SOC_DAPM_REGULATOR_SUPPLY("DVDD", 0, 0),
229*4882a593Smuzhiyun SND_SOC_DAPM_CLOCK_SUPPLY("mclk"),
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun static const struct snd_soc_dapm_route max9860_dapm_routes[] = {
233*4882a593Smuzhiyun 	{ "ADCL", NULL, "MICL" },
234*4882a593Smuzhiyun 	{ "ADCR", NULL, "MICR" },
235*4882a593Smuzhiyun 	{ "AIFOUTL", NULL, "ADCL" },
236*4882a593Smuzhiyun 	{ "AIFOUTR", NULL, "ADCR" },
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	{ "DAC", NULL, "AIFINL" },
239*4882a593Smuzhiyun 	{ "DAC", NULL, "AIFINR" },
240*4882a593Smuzhiyun 	{ "OUT", NULL, "DAC" },
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	{ "Supply", NULL, "AVDD" },
243*4882a593Smuzhiyun 	{ "Supply", NULL, "DVDD" },
244*4882a593Smuzhiyun 	{ "Supply", NULL, "mclk" },
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	{ "DAC", NULL, "Supply" },
247*4882a593Smuzhiyun 	{ "ADCL", NULL, "Supply" },
248*4882a593Smuzhiyun 	{ "ADCR", NULL, "Supply" },
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun 
max9860_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)251*4882a593Smuzhiyun static int max9860_hw_params(struct snd_pcm_substream *substream,
252*4882a593Smuzhiyun 			     struct snd_pcm_hw_params *params,
253*4882a593Smuzhiyun 			     struct snd_soc_dai *dai)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
256*4882a593Smuzhiyun 	struct max9860_priv *max9860 = snd_soc_component_get_drvdata(component);
257*4882a593Smuzhiyun 	u8 master;
258*4882a593Smuzhiyun 	u8 ifc1a = 0;
259*4882a593Smuzhiyun 	u8 ifc1b = 0;
260*4882a593Smuzhiyun 	u8 sysclk = 0;
261*4882a593Smuzhiyun 	unsigned long n;
262*4882a593Smuzhiyun 	int ret;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	dev_dbg(component->dev, "hw_params %u Hz, %u channels\n",
265*4882a593Smuzhiyun 		params_rate(params),
266*4882a593Smuzhiyun 		params_channels(params));
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	if (params_channels(params) == 2)
269*4882a593Smuzhiyun 		ifc1b |= MAX9860_ST;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	switch (max9860->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
272*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
273*4882a593Smuzhiyun 		master = 0;
274*4882a593Smuzhiyun 		break;
275*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
276*4882a593Smuzhiyun 		master = MAX9860_MASTER;
277*4882a593Smuzhiyun 		break;
278*4882a593Smuzhiyun 	default:
279*4882a593Smuzhiyun 		return -EINVAL;
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 	ifc1a |= master;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	if (master) {
284*4882a593Smuzhiyun 		if (params_width(params) * params_channels(params) > 48)
285*4882a593Smuzhiyun 			ifc1b |= MAX9860_BSEL_64X;
286*4882a593Smuzhiyun 		else
287*4882a593Smuzhiyun 			ifc1b |= MAX9860_BSEL_48X;
288*4882a593Smuzhiyun 	}
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
291*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
292*4882a593Smuzhiyun 		ifc1a |= MAX9860_DDLY;
293*4882a593Smuzhiyun 		ifc1b |= MAX9860_ADLY;
294*4882a593Smuzhiyun 		break;
295*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_LEFT_J:
296*4882a593Smuzhiyun 		ifc1a |= MAX9860_WCI;
297*4882a593Smuzhiyun 		break;
298*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_DSP_A:
299*4882a593Smuzhiyun 		if (params_width(params) != 16) {
300*4882a593Smuzhiyun 			dev_err(component->dev,
301*4882a593Smuzhiyun 				"DSP_A works for 16 bits per sample only.\n");
302*4882a593Smuzhiyun 			return -EINVAL;
303*4882a593Smuzhiyun 		}
304*4882a593Smuzhiyun 		ifc1a |= MAX9860_DDLY | MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
305*4882a593Smuzhiyun 		ifc1b |= MAX9860_ADLY;
306*4882a593Smuzhiyun 		break;
307*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_DSP_B:
308*4882a593Smuzhiyun 		if (params_width(params) != 16) {
309*4882a593Smuzhiyun 			dev_err(component->dev,
310*4882a593Smuzhiyun 				"DSP_B works for 16 bits per sample only.\n");
311*4882a593Smuzhiyun 			return -EINVAL;
312*4882a593Smuzhiyun 		}
313*4882a593Smuzhiyun 		ifc1a |= MAX9860_WCI | MAX9860_HIZ | MAX9860_TDM;
314*4882a593Smuzhiyun 		break;
315*4882a593Smuzhiyun 	default:
316*4882a593Smuzhiyun 		return -EINVAL;
317*4882a593Smuzhiyun 	}
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	switch (max9860->fmt & SND_SOC_DAIFMT_INV_MASK) {
320*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_NF:
321*4882a593Smuzhiyun 		break;
322*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_IF:
323*4882a593Smuzhiyun 		switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
324*4882a593Smuzhiyun 		case SND_SOC_DAIFMT_DSP_A:
325*4882a593Smuzhiyun 		case SND_SOC_DAIFMT_DSP_B:
326*4882a593Smuzhiyun 			return -EINVAL;
327*4882a593Smuzhiyun 		}
328*4882a593Smuzhiyun 		ifc1a ^= MAX9860_WCI;
329*4882a593Smuzhiyun 		break;
330*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_IF:
331*4882a593Smuzhiyun 		switch (max9860->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
332*4882a593Smuzhiyun 		case SND_SOC_DAIFMT_DSP_A:
333*4882a593Smuzhiyun 		case SND_SOC_DAIFMT_DSP_B:
334*4882a593Smuzhiyun 			return -EINVAL;
335*4882a593Smuzhiyun 		}
336*4882a593Smuzhiyun 		ifc1a ^= MAX9860_WCI;
337*4882a593Smuzhiyun 		fallthrough;
338*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_NF:
339*4882a593Smuzhiyun 		ifc1a ^= MAX9860_DBCI;
340*4882a593Smuzhiyun 		ifc1b ^= MAX9860_ABCI;
341*4882a593Smuzhiyun 		break;
342*4882a593Smuzhiyun 	default:
343*4882a593Smuzhiyun 		return -EINVAL;
344*4882a593Smuzhiyun 	}
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	dev_dbg(component->dev, "IFC1A  %02x\n", ifc1a);
347*4882a593Smuzhiyun 	ret = regmap_write(max9860->regmap, MAX9860_IFC1A, ifc1a);
348*4882a593Smuzhiyun 	if (ret) {
349*4882a593Smuzhiyun 		dev_err(component->dev, "Failed to set IFC1A: %d\n", ret);
350*4882a593Smuzhiyun 		return ret;
351*4882a593Smuzhiyun 	}
352*4882a593Smuzhiyun 	dev_dbg(component->dev, "IFC1B  %02x\n", ifc1b);
353*4882a593Smuzhiyun 	ret = regmap_write(max9860->regmap, MAX9860_IFC1B, ifc1b);
354*4882a593Smuzhiyun 	if (ret) {
355*4882a593Smuzhiyun 		dev_err(component->dev, "Failed to set IFC1B: %d\n", ret);
356*4882a593Smuzhiyun 		return ret;
357*4882a593Smuzhiyun 	}
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	/*
360*4882a593Smuzhiyun 	 * Check if Integer Clock Mode is possible, but avoid it in slave mode
361*4882a593Smuzhiyun 	 * since we then do not know if lrclk is derived from pclk and the
362*4882a593Smuzhiyun 	 * datasheet mentions that the frequencies have to match exactly in
363*4882a593Smuzhiyun 	 * order for this to work.
364*4882a593Smuzhiyun 	 */
365*4882a593Smuzhiyun 	if (params_rate(params) == 8000 || params_rate(params) == 16000) {
366*4882a593Smuzhiyun 		if (master) {
367*4882a593Smuzhiyun 			switch (max9860->pclk_rate) {
368*4882a593Smuzhiyun 			case 12000000:
369*4882a593Smuzhiyun 				sysclk = MAX9860_FREQ_12MHZ;
370*4882a593Smuzhiyun 				break;
371*4882a593Smuzhiyun 			case 13000000:
372*4882a593Smuzhiyun 				sysclk = MAX9860_FREQ_13MHZ;
373*4882a593Smuzhiyun 				break;
374*4882a593Smuzhiyun 			case 19200000:
375*4882a593Smuzhiyun 				sysclk = MAX9860_FREQ_19_2MHZ;
376*4882a593Smuzhiyun 				break;
377*4882a593Smuzhiyun 			default:
378*4882a593Smuzhiyun 				/*
379*4882a593Smuzhiyun 				 * Integer Clock Mode not possible. Leave
380*4882a593Smuzhiyun 				 * sysclk at zero and fall through to the
381*4882a593Smuzhiyun 				 * code below for PLL mode.
382*4882a593Smuzhiyun 				 */
383*4882a593Smuzhiyun 				break;
384*4882a593Smuzhiyun 			}
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 			if (sysclk && params_rate(params) == 16000)
387*4882a593Smuzhiyun 				sysclk |= MAX9860_16KHZ;
388*4882a593Smuzhiyun 		}
389*4882a593Smuzhiyun 	}
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	/*
392*4882a593Smuzhiyun 	 * Largest possible n:
393*4882a593Smuzhiyun 	 *    65536 * 96 * 48kHz / 10MHz -> 30199
394*4882a593Smuzhiyun 	 * Smallest possible n:
395*4882a593Smuzhiyun 	 *    65536 * 96 *  8kHz / 20MHz -> 2517
396*4882a593Smuzhiyun 	 * Both fit nicely in the available 15 bits, no need to apply any mask.
397*4882a593Smuzhiyun 	 */
398*4882a593Smuzhiyun 	n = DIV_ROUND_CLOSEST_ULL(65536ULL * 96 * params_rate(params),
399*4882a593Smuzhiyun 				  max9860->pclk_rate);
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	if (!sysclk) {
402*4882a593Smuzhiyun 		/* PLL mode */
403*4882a593Smuzhiyun 		if (params_rate(params) > 24000)
404*4882a593Smuzhiyun 			sysclk |= MAX9860_16KHZ;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 		if (!master)
407*4882a593Smuzhiyun 			n |= 1; /* trigger rapid pll lock mode */
408*4882a593Smuzhiyun 	}
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	sysclk |= max9860->psclk;
411*4882a593Smuzhiyun 	dev_dbg(component->dev, "SYSCLK %02x\n", sysclk);
412*4882a593Smuzhiyun 	ret = regmap_write(max9860->regmap,
413*4882a593Smuzhiyun 			   MAX9860_SYSCLK, sysclk);
414*4882a593Smuzhiyun 	if (ret) {
415*4882a593Smuzhiyun 		dev_err(component->dev, "Failed to set SYSCLK: %d\n", ret);
416*4882a593Smuzhiyun 		return ret;
417*4882a593Smuzhiyun 	}
418*4882a593Smuzhiyun 	dev_dbg(component->dev, "N %lu\n", n);
419*4882a593Smuzhiyun 	ret = regmap_write(max9860->regmap,
420*4882a593Smuzhiyun 			   MAX9860_AUDIOCLKHIGH, n >> 8);
421*4882a593Smuzhiyun 	if (ret) {
422*4882a593Smuzhiyun 		dev_err(component->dev, "Failed to set NHI: %d\n", ret);
423*4882a593Smuzhiyun 		return ret;
424*4882a593Smuzhiyun 	}
425*4882a593Smuzhiyun 	ret = regmap_write(max9860->regmap,
426*4882a593Smuzhiyun 			   MAX9860_AUDIOCLKLOW, n & 0xff);
427*4882a593Smuzhiyun 	if (ret) {
428*4882a593Smuzhiyun 		dev_err(component->dev, "Failed to set NLO: %d\n", ret);
429*4882a593Smuzhiyun 		return ret;
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	if (!master) {
433*4882a593Smuzhiyun 		dev_dbg(component->dev, "Enable PLL\n");
434*4882a593Smuzhiyun 		ret = regmap_update_bits(max9860->regmap, MAX9860_AUDIOCLKHIGH,
435*4882a593Smuzhiyun 					 MAX9860_PLL, MAX9860_PLL);
436*4882a593Smuzhiyun 		if (ret) {
437*4882a593Smuzhiyun 			dev_err(component->dev, "Failed to enable PLL: %d\n",
438*4882a593Smuzhiyun 				ret);
439*4882a593Smuzhiyun 			return ret;
440*4882a593Smuzhiyun 		}
441*4882a593Smuzhiyun 	}
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	return 0;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun 
max9860_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)446*4882a593Smuzhiyun static int max9860_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
449*4882a593Smuzhiyun 	struct max9860_priv *max9860 = snd_soc_component_get_drvdata(component);
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
452*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
453*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
454*4882a593Smuzhiyun 		max9860->fmt = fmt;
455*4882a593Smuzhiyun 		return 0;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	default:
458*4882a593Smuzhiyun 		return -EINVAL;
459*4882a593Smuzhiyun 	}
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun static const struct snd_soc_dai_ops max9860_dai_ops = {
463*4882a593Smuzhiyun 	.hw_params = max9860_hw_params,
464*4882a593Smuzhiyun 	.set_fmt = max9860_set_fmt,
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun static struct snd_soc_dai_driver max9860_dai = {
468*4882a593Smuzhiyun 	.name = "max9860-hifi",
469*4882a593Smuzhiyun 	.playback = {
470*4882a593Smuzhiyun 		.stream_name = "Playback",
471*4882a593Smuzhiyun 		.channels_min = 1,
472*4882a593Smuzhiyun 		.channels_max = 2,
473*4882a593Smuzhiyun 		.rates = SNDRV_PCM_RATE_CONTINUOUS,
474*4882a593Smuzhiyun 		.rate_min = 8000,
475*4882a593Smuzhiyun 		.rate_max = 48000,
476*4882a593Smuzhiyun 		.formats = SNDRV_PCM_FMTBIT_S16_LE |
477*4882a593Smuzhiyun 			   SNDRV_PCM_FMTBIT_S24_LE |
478*4882a593Smuzhiyun 			   SNDRV_PCM_FMTBIT_S32_LE,
479*4882a593Smuzhiyun 	},
480*4882a593Smuzhiyun 	.capture = {
481*4882a593Smuzhiyun 		.stream_name = "Capture",
482*4882a593Smuzhiyun 		.channels_min = 1,
483*4882a593Smuzhiyun 		.channels_max = 2,
484*4882a593Smuzhiyun 		.rates = SNDRV_PCM_RATE_CONTINUOUS,
485*4882a593Smuzhiyun 		.rate_min = 8000,
486*4882a593Smuzhiyun 		.rate_max = 48000,
487*4882a593Smuzhiyun 		.formats = SNDRV_PCM_FMTBIT_S16_LE |
488*4882a593Smuzhiyun 			   SNDRV_PCM_FMTBIT_S24_LE |
489*4882a593Smuzhiyun 			   SNDRV_PCM_FMTBIT_S32_LE,
490*4882a593Smuzhiyun 	},
491*4882a593Smuzhiyun 	.ops = &max9860_dai_ops,
492*4882a593Smuzhiyun 	.symmetric_rates = 1,
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun 
max9860_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)495*4882a593Smuzhiyun static int max9860_set_bias_level(struct snd_soc_component *component,
496*4882a593Smuzhiyun 				  enum snd_soc_bias_level level)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun 	struct max9860_priv *max9860 = dev_get_drvdata(component->dev);
499*4882a593Smuzhiyun 	int ret;
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	switch (level) {
502*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
503*4882a593Smuzhiyun 	case SND_SOC_BIAS_PREPARE:
504*4882a593Smuzhiyun 		break;
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
507*4882a593Smuzhiyun 		ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
508*4882a593Smuzhiyun 					 MAX9860_SHDN, MAX9860_SHDN);
509*4882a593Smuzhiyun 		if (ret) {
510*4882a593Smuzhiyun 			dev_err(component->dev, "Failed to remove SHDN: %d\n",
511*4882a593Smuzhiyun 				ret);
512*4882a593Smuzhiyun 			return ret;
513*4882a593Smuzhiyun 		}
514*4882a593Smuzhiyun 		break;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	case SND_SOC_BIAS_OFF:
517*4882a593Smuzhiyun 		ret = regmap_update_bits(max9860->regmap, MAX9860_PWRMAN,
518*4882a593Smuzhiyun 					 MAX9860_SHDN, 0);
519*4882a593Smuzhiyun 		if (ret) {
520*4882a593Smuzhiyun 			dev_err(component->dev, "Failed to request SHDN: %d\n",
521*4882a593Smuzhiyun 				ret);
522*4882a593Smuzhiyun 			return ret;
523*4882a593Smuzhiyun 		}
524*4882a593Smuzhiyun 		break;
525*4882a593Smuzhiyun 	}
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	return 0;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun static const struct snd_soc_component_driver max9860_component_driver = {
531*4882a593Smuzhiyun 	.set_bias_level		= max9860_set_bias_level,
532*4882a593Smuzhiyun 	.controls		= max9860_controls,
533*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(max9860_controls),
534*4882a593Smuzhiyun 	.dapm_widgets		= max9860_dapm_widgets,
535*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(max9860_dapm_widgets),
536*4882a593Smuzhiyun 	.dapm_routes		= max9860_dapm_routes,
537*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(max9860_dapm_routes),
538*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
539*4882a593Smuzhiyun 	.endianness		= 1,
540*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
541*4882a593Smuzhiyun };
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun #ifdef CONFIG_PM
max9860_suspend(struct device * dev)544*4882a593Smuzhiyun static int max9860_suspend(struct device *dev)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun 	struct max9860_priv *max9860 = dev_get_drvdata(dev);
547*4882a593Smuzhiyun 	int ret;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
550*4882a593Smuzhiyun 				 MAX9860_PSCLK, MAX9860_PSCLK_OFF);
551*4882a593Smuzhiyun 	if (ret) {
552*4882a593Smuzhiyun 		dev_err(dev, "Failed to disable clock: %d\n", ret);
553*4882a593Smuzhiyun 		return ret;
554*4882a593Smuzhiyun 	}
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	regulator_disable(max9860->dvddio);
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	return 0;
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun 
max9860_resume(struct device * dev)561*4882a593Smuzhiyun static int max9860_resume(struct device *dev)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun 	struct max9860_priv *max9860 = dev_get_drvdata(dev);
564*4882a593Smuzhiyun 	int ret;
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	ret = regulator_enable(max9860->dvddio);
567*4882a593Smuzhiyun 	if (ret) {
568*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
569*4882a593Smuzhiyun 		return ret;
570*4882a593Smuzhiyun 	}
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	regcache_cache_only(max9860->regmap, false);
573*4882a593Smuzhiyun 	ret = regcache_sync(max9860->regmap);
574*4882a593Smuzhiyun 	if (ret) {
575*4882a593Smuzhiyun 		dev_err(dev, "Failed to sync cache: %d\n", ret);
576*4882a593Smuzhiyun 		return ret;
577*4882a593Smuzhiyun 	}
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	ret = regmap_update_bits(max9860->regmap, MAX9860_SYSCLK,
580*4882a593Smuzhiyun 				 MAX9860_PSCLK, max9860->psclk);
581*4882a593Smuzhiyun 	if (ret) {
582*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable clock: %d\n", ret);
583*4882a593Smuzhiyun 		return ret;
584*4882a593Smuzhiyun 	}
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	return 0;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun #endif
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun static const struct dev_pm_ops max9860_pm_ops = {
591*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(max9860_suspend, max9860_resume, NULL)
592*4882a593Smuzhiyun };
593*4882a593Smuzhiyun 
max9860_probe(struct i2c_client * i2c)594*4882a593Smuzhiyun static int max9860_probe(struct i2c_client *i2c)
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun 	struct device *dev = &i2c->dev;
597*4882a593Smuzhiyun 	struct max9860_priv *max9860;
598*4882a593Smuzhiyun 	int ret;
599*4882a593Smuzhiyun 	struct clk *mclk;
600*4882a593Smuzhiyun 	unsigned long mclk_rate;
601*4882a593Smuzhiyun 	int i;
602*4882a593Smuzhiyun 	int intr;
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	max9860 = devm_kzalloc(dev, sizeof(struct max9860_priv), GFP_KERNEL);
605*4882a593Smuzhiyun 	if (!max9860)
606*4882a593Smuzhiyun 		return -ENOMEM;
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun 	max9860->dvddio = devm_regulator_get(dev, "DVDDIO");
609*4882a593Smuzhiyun 	if (IS_ERR(max9860->dvddio)) {
610*4882a593Smuzhiyun 		ret = PTR_ERR(max9860->dvddio);
611*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
612*4882a593Smuzhiyun 			dev_err(dev, "Failed to get DVDDIO supply: %d\n", ret);
613*4882a593Smuzhiyun 		return ret;
614*4882a593Smuzhiyun 	}
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	max9860->dvddio_nb.notifier_call = max9860_dvddio_event;
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	ret = devm_regulator_register_notifier(max9860->dvddio,
619*4882a593Smuzhiyun 					       &max9860->dvddio_nb);
620*4882a593Smuzhiyun 	if (ret)
621*4882a593Smuzhiyun 		dev_err(dev, "Failed to register DVDDIO notifier: %d\n", ret);
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	ret = regulator_enable(max9860->dvddio);
624*4882a593Smuzhiyun 	if (ret != 0) {
625*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable DVDDIO: %d\n", ret);
626*4882a593Smuzhiyun 		return ret;
627*4882a593Smuzhiyun 	}
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 	max9860->regmap = devm_regmap_init_i2c(i2c, &max9860_regmap);
630*4882a593Smuzhiyun 	if (IS_ERR(max9860->regmap)) {
631*4882a593Smuzhiyun 		ret = PTR_ERR(max9860->regmap);
632*4882a593Smuzhiyun 		goto err_regulator;
633*4882a593Smuzhiyun 	}
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	dev_set_drvdata(dev, max9860);
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	/*
638*4882a593Smuzhiyun 	 * mclk has to be in the 10MHz to 60MHz range.
639*4882a593Smuzhiyun 	 * psclk is used to scale mclk into pclk so that
640*4882a593Smuzhiyun 	 * pclk is in the 10MHz to 20MHz range.
641*4882a593Smuzhiyun 	 */
642*4882a593Smuzhiyun 	mclk = clk_get(dev, "mclk");
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	if (IS_ERR(mclk)) {
645*4882a593Smuzhiyun 		ret = PTR_ERR(mclk);
646*4882a593Smuzhiyun 		if (ret != -EPROBE_DEFER)
647*4882a593Smuzhiyun 			dev_err(dev, "Failed to get MCLK: %d\n", ret);
648*4882a593Smuzhiyun 		goto err_regulator;
649*4882a593Smuzhiyun 	}
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	mclk_rate = clk_get_rate(mclk);
652*4882a593Smuzhiyun 	clk_put(mclk);
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	if (mclk_rate > 60000000 || mclk_rate < 10000000) {
655*4882a593Smuzhiyun 		dev_err(dev, "Bad mclk %luHz (needs 10MHz - 60MHz)\n",
656*4882a593Smuzhiyun 			mclk_rate);
657*4882a593Smuzhiyun 		ret = -EINVAL;
658*4882a593Smuzhiyun 		goto err_regulator;
659*4882a593Smuzhiyun 	}
660*4882a593Smuzhiyun 	if (mclk_rate >= 40000000)
661*4882a593Smuzhiyun 		max9860->psclk = 3;
662*4882a593Smuzhiyun 	else if (mclk_rate >= 20000000)
663*4882a593Smuzhiyun 		max9860->psclk = 2;
664*4882a593Smuzhiyun 	else
665*4882a593Smuzhiyun 		max9860->psclk = 1;
666*4882a593Smuzhiyun 	max9860->pclk_rate = mclk_rate >> (max9860->psclk - 1);
667*4882a593Smuzhiyun 	max9860->psclk <<= MAX9860_PSCLK_SHIFT;
668*4882a593Smuzhiyun 	dev_dbg(dev, "mclk %lu pclk %lu\n", mclk_rate, max9860->pclk_rate);
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	regcache_cache_bypass(max9860->regmap, true);
671*4882a593Smuzhiyun 	for (i = 0; i < max9860_regmap.num_reg_defaults; ++i) {
672*4882a593Smuzhiyun 		ret = regmap_write(max9860->regmap,
673*4882a593Smuzhiyun 				   max9860_regmap.reg_defaults[i].reg,
674*4882a593Smuzhiyun 				   max9860_regmap.reg_defaults[i].def);
675*4882a593Smuzhiyun 		if (ret) {
676*4882a593Smuzhiyun 			dev_err(dev, "Failed to initialize register %u: %d\n",
677*4882a593Smuzhiyun 				max9860_regmap.reg_defaults[i].reg, ret);
678*4882a593Smuzhiyun 			goto err_regulator;
679*4882a593Smuzhiyun 		}
680*4882a593Smuzhiyun 	}
681*4882a593Smuzhiyun 	regcache_cache_bypass(max9860->regmap, false);
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	ret = regmap_read(max9860->regmap, MAX9860_INTRSTATUS, &intr);
684*4882a593Smuzhiyun 	if (ret) {
685*4882a593Smuzhiyun 		dev_err(dev, "Failed to clear INTRSTATUS: %d\n", ret);
686*4882a593Smuzhiyun 		goto err_regulator;
687*4882a593Smuzhiyun 	}
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun 	pm_runtime_set_active(dev);
690*4882a593Smuzhiyun 	pm_runtime_enable(dev);
691*4882a593Smuzhiyun 	pm_runtime_idle(dev);
692*4882a593Smuzhiyun 
693*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(dev, &max9860_component_driver,
694*4882a593Smuzhiyun 					      &max9860_dai, 1);
695*4882a593Smuzhiyun 	if (ret) {
696*4882a593Smuzhiyun 		dev_err(dev, "Failed to register CODEC: %d\n", ret);
697*4882a593Smuzhiyun 		goto err_pm;
698*4882a593Smuzhiyun 	}
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	return 0;
701*4882a593Smuzhiyun 
702*4882a593Smuzhiyun err_pm:
703*4882a593Smuzhiyun 	pm_runtime_disable(dev);
704*4882a593Smuzhiyun err_regulator:
705*4882a593Smuzhiyun 	regulator_disable(max9860->dvddio);
706*4882a593Smuzhiyun 	return ret;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun 
max9860_remove(struct i2c_client * i2c)709*4882a593Smuzhiyun static int max9860_remove(struct i2c_client *i2c)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun 	struct device *dev = &i2c->dev;
712*4882a593Smuzhiyun 	struct max9860_priv *max9860 = dev_get_drvdata(dev);
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	pm_runtime_disable(dev);
715*4882a593Smuzhiyun 	regulator_disable(max9860->dvddio);
716*4882a593Smuzhiyun 	return 0;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun static const struct i2c_device_id max9860_i2c_id[] = {
720*4882a593Smuzhiyun 	{ "max9860", },
721*4882a593Smuzhiyun 	{ }
722*4882a593Smuzhiyun };
723*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max9860_i2c_id);
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun static const struct of_device_id max9860_of_match[] = {
726*4882a593Smuzhiyun 	{ .compatible = "maxim,max9860", },
727*4882a593Smuzhiyun 	{ }
728*4882a593Smuzhiyun };
729*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max9860_of_match);
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun static struct i2c_driver max9860_i2c_driver = {
732*4882a593Smuzhiyun 	.probe_new      = max9860_probe,
733*4882a593Smuzhiyun 	.remove         = max9860_remove,
734*4882a593Smuzhiyun 	.id_table       = max9860_i2c_id,
735*4882a593Smuzhiyun 	.driver         = {
736*4882a593Smuzhiyun 		.name           = "max9860",
737*4882a593Smuzhiyun 		.of_match_table = max9860_of_match,
738*4882a593Smuzhiyun 		.pm             = &max9860_pm_ops,
739*4882a593Smuzhiyun 	},
740*4882a593Smuzhiyun };
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun module_i2c_driver(max9860_i2c_driver);
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC MAX9860 Mono Audio Voice Codec driver");
745*4882a593Smuzhiyun MODULE_AUTHOR("Peter Rosin <peda@axentia.se>");
746*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
747