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/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.c37 #define TOPOLOGY_TEST_OK 0
47 /* 0 1 2 3 */
50 { 1, 1, 0, 0 }, /* USB3H */
51 { 1, 1, 1, 0 }, /* USB3D */
53 { 1, 0, 0, 0 }, /* QSGMII */
54 { 4, 0, 0, 0 }, /* XAUI */
55 { 2, 0, 0, 0 } /* RXAUI */
62 u8 serdes_unit_count[MAX_UNITS_ID] = { 0 };
66 /* 0 1 2 3 4 5 6 */
67 { 0x1, 0x1, NA, NA, NA, NA, NA }, /* PEX0 */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
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H A Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
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H A Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
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H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
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H A Dsmu_7_0_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/
H A Dpasemi_nand.c26 #define LBICTRL_LPCCTL_NR 0x00004000
37 while (len > 0x800) { in pasemi_read_buf()
38 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
39 buf += 0x800; in pasemi_read_buf()
40 len -= 0x800; in pasemi_read_buf()
48 while (len > 0x800) { in pasemi_write_buf()
49 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
50 buf += 0x800; in pasemi_write_buf()
51 len -= 0x800; in pasemi_write_buf()
83 return 0; in pasemi_attach_chip()
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H A Dcs553x_nand.c11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
30 #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
31 #define CAP_CS5535 0x2df000ULL
32 #define CAP_CS5536 0x5df500ULL
35 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
36 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
37 #define MSR_NANDF_RSVD 0x5140001d /* Reserved */
40 #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
41 #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
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/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Drv1106_pm.h9 #define RV1106_WAKEUP_TO_SYSTEM_RESET 0
11 #define RV1106_PERIGRF_OFFSET 0x0
12 #define RV1106_VENCGRF_OFFSET 0x10000
13 #define RV1106_NPUGRF_OFFSET 0x18000
14 #define RV1106_PMUGRF_OFFSET 0x20000
15 #define RV1106_DDRGRF_OFFSET 0x30000
16 #define RV1106_COREGRF_OFFSET 0x40000
17 #define RV1106_VIGRF_OFFSET 0x50000
18 #define RV1106_VOGRF_OFFSET 0x60000
20 #define RV1106_PERISGRF_OFFSET 0x70000
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/
H A Dnouveau_reg.h3 #define NV04_PFB_BOOT_0 0x00100000
4 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
9 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
10 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
11 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
12 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgf119.c45 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800)); in gf119_disp_super()
49 if (disp->super & 0x00000001) { in gf119_disp_super()
50 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); in gf119_disp_super()
53 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
58 if (disp->super & 0x00000002) { in gf119_disp_super()
60 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
66 if (!(mask[head->id] & 0x00010000)) in gf119_disp_super()
71 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
76 if (disp->super & 0x00000004) { in gf119_disp_super()
78 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
[all …]
/OK3568_Linux_fs/kernel/arch/riscv/kernel/
H A Dmodule.c37 return 0; in apply_r_riscv_32_rela()
43 return 0; in apply_r_riscv_64_rela()
50 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
51 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
52 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
53 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
55 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
56 return 0; in apply_r_riscv_branch_rela()
63 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
64 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dsam9x60.dtsi36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
47 reg = <0x20000000 0x10000000>;
53 #clock-cells = <0>;
58 #clock-cells = <0>;
64 reg = <0x00300000 0x100000>;
67 ranges = <0 0x00300000 0x100000>;
78 #size-cells = <0>;
80 reg = <0x00500000 0x100000
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/rtl8188eu/include/
H A Dhal8188e_phy_reg.h11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
14 /* 3. RF register 0x00-2E */
19 /* 3. Page8(0x800) */
20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
23 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
24 #define rFPGA0_XA_HSSIParameter2 0x824
25 #define rFPGA0_XB_HSSIParameter1 0x828
26 #define rFPGA0_XB_HSSIParameter2 0x82c
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Dmediatek-vcodec.txt32 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
33 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
34 <0 0x16021000 0 0x800>, /*VDEC_LD*/
35 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
36 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
37 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
38 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
39 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
40 <0 0x16026800 0 0x800>, /*VP8_VD*/
41 <0 0x16027000 0 0x800>, /*VP6_VD*/
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/cpu-sh4a/cpu/
H A Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
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/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
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/OK3568_Linux_fs/u-boot/board/freescale/mx6sabreauto/
H A DREADME60 # load mmc 0:1 ${fdt_addr} imx6dl-sabreauto.dtb
64 # load mmc 0:1 ${loadaddr} uImage
68 # mmc write ${loadaddr} 0x1000 0x4000
78 - Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
80 # mmc write 18000000 0x800 0x800
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/hsi/
H A Domap-ssi.txt37 0 and 1 (in this order).
55 reg = <0x48058000 0x1000>,
56 <0x48059000 0x1000>;
77 reg = <0x4805a000 0x800>,
78 <0x4805a800 0x800>;
92 reg = <0x4805b000 0x800>,
93 <0x4805b800 0x800>;
/OK3568_Linux_fs/kernel/drivers/rkflash/
H A Dnandc.h13 #define NANDC_READ 0
15 #define RK3326_NANDC_VER 0x56393030
19 NC_IRQ_DMA = 0,
27 NC_BCH_70 = 0,
36 unsigned cs : 8; /* bits[0:7] */
149 unsigned bch_mode : 1; /* 0-16bit/1KB, 1-24bit/1KB */
251 #define NANDC_FMCTL 0x0
252 #define NANDC_FMWAIT 0x4
253 #define NANDC_FLCTL 0x8
254 #define NANDC_BCHCTL 0xc
[all …]
/OK3568_Linux_fs/u-boot/drivers/rkflash/
H A Dnandc.h15 #define NANDC_READ 0
17 #define RK3326_NANDC_VER 0x56393030
21 NC_IRQ_DMA = 0,
29 NC_BCH_70 = 0,
38 unsigned cs : 8; /* bits[0:7] */
151 unsigned bch_mode : 1; /* 0-16bit/1KB, 1-24bit/1KB */
253 #define NANDC_FMCTL 0x0
254 #define NANDC_FMWAIT 0x4
255 #define NANDC_FLCTL 0x8
256 #define NANDC_BCHCTL 0xc
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/OK3568_Linux_fs/u-boot/board/freescale/mx6sabresd/
H A DREADME48 => mmc partconf 2 1 0 0
52 => ums 0 mmc 2
99 # mmc write ${loadaddr} 0x1000 0x4000
109 - Write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
111 # mmc write 18000000 0x800 0x800
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/include/
H A DHal8188EPhyReg.h24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
27 // 3. RF register 0x00-2E
35 // 1. Page1(0x100)
37 #define rPMAC_Reset 0x100
38 #define rPMAC_TxStart 0x104
39 #define rPMAC_TxLegacySIG 0x108
40 #define rPMAC_TxHTSIG1 0x10c
41 #define rPMAC_TxHTSIG2 0x110
42 #define rPMAC_PHYDebug 0x114
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bu/include/
H A DHal8188EPhyReg.h24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
27 // 3. RF register 0x00-2E
35 // 1. Page1(0x100)
37 #define rPMAC_Reset 0x100
38 #define rPMAC_TxStart 0x104
39 #define rPMAC_TxLegacySIG 0x108
40 #define rPMAC_TxHTSIG1 0x10c
41 #define rPMAC_TxHTSIG2 0x110
42 #define rPMAC_PHYDebug 0x114
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
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