1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2 /*
3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4 */
5
6 #ifndef __MACH_ROCKCHIP_RV1106_PM_H
7 #define __MACH_ROCKCHIP_RV1106_PM_H
8
9 #define RV1106_WAKEUP_TO_SYSTEM_RESET 0
10
11 #define RV1106_PERIGRF_OFFSET 0x0
12 #define RV1106_VENCGRF_OFFSET 0x10000
13 #define RV1106_NPUGRF_OFFSET 0x18000
14 #define RV1106_PMUGRF_OFFSET 0x20000
15 #define RV1106_DDRGRF_OFFSET 0x30000
16 #define RV1106_COREGRF_OFFSET 0x40000
17 #define RV1106_VIGRF_OFFSET 0x50000
18 #define RV1106_VOGRF_OFFSET 0x60000
19
20 #define RV1106_PERISGRF_OFFSET 0x70000
21 #define RV1106_VISGRF_OFFSET 0x72000
22 #define RV1106_NPUSGRF_OFFSET 0x74000
23 #define RV1106_CORESGRF_OFFSET 0x76000
24 #define RV1106_VENCSGRF_OFFSET 0x78000
25 #define RV1106_VOSGRF_OFFSET 0x7a000
26 #define RV1106_PMUSGRF_OFFSET 0x80000
27
28 #define RV1106_GIC_OFFSET 0x1f0000
29 #define RV1106_HPTIMER_OFFSET 0x2f0000
30 #define RV1106_PMU_OFFSET 0x300000
31 #define RV1106_GPIO0_OFFSET 0x380000
32 #define RV1106_GPIO0IOC_OFFSET 0x388000
33 #define RV1106_PMUPVTM_OFFSET 0x390000
34
35 #define RV1106_PMUCRU_OFFSET 0x3a0000
36 #define RV1106_CRU_OFFSET 0x3b0000
37 #define RV1106_PERICRU_OFFSET 0x3b2000
38 #define RV1106_VICRU_OFFSET 0x3b4000
39 #define RV1106_NPUCRU_OFFSET 0x3b6000
40 #define RV1106_CORECRU_OFFSET 0x3b8000
41 #define RV1106_VENCCRU_OFFSET 0x3ba000
42 #define RV1106_VOCRU_OFFSET 0x3bc000
43
44 #define RV1106_UART2_OFFSET 0x4c0000
45
46 #define RV1106_GPIO1_OFFSET 0x530000
47 #define RV1106_GPIO1IOC_OFFSET 0x538000
48 #define RV1106_GPIO2_OFFSET 0x540000
49 #define RV1106_GPIO2IOC_OFFSET 0x548000
50 #define RV1106_GPIO3_OFFSET 0x550000
51 #define RV1106_GPIO3IOC_OFFSET 0x558000
52 #define RV1106_GPIO4_OFFSET 0x560000
53 #define RV1106_GPIO4IOC_OFFSET 0x568000
54
55 #define RV1106_NSTIMER_OFFSET 0x580000
56 #define RV1106_STIMER_OFFSET 0x590000
57 #define RV1106_PMUSRAM_OFFSET 0x670000
58 #define RV1106_DDRC_OFFSET 0x800000
59 #define RV1106_FW_DDR_OFFSET 0x900000
60 #define RV1106_FW_SRAM_OFFSET 0x910000
61
62 #define RV1106_DEV_REG_BASE 0xff000000
63 #define RV1106_DEV_REG_SIZE 0x920000
64
65 #define RV1106_PMUSRAM_BASE \
66 (RV1106_DEV_REG_BASE + RV1106_PMUSRAM_OFFSET)
67
68 /* cru */
69 #define RV1106_CRU_PLL_CON(pll_id, i) ((pll_id) * 0x20 + (i) * 4)
70 #define RV1106_CRU_MODE_CON00 0x280
71 #define RV1106_CRU_GATE_CON(i) (0x800 + (i) * 4)
72 #define RV1106_CRU_GATE_CON_NUM 4
73
74 #define CRU_PLLCON1_PWRDOWN BIT(13)
75 #define CRU_PLLCON1_LOCK_STATUS BIT(10)
76
77 #define RV1106_PMUCRU_GATE_CON(i) (0x800 + (i) * 4)
78 #define RV1106_PMUCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
79 #define RV1106_PMUCRU_GATE_CON_NUM 3
80
81 #define RV1106_PERICRU_GATE_CON(i) (0x800 + (i) * 4)
82 #define RV1106_PERICRU_CLKSEL_CON(i) (0x300 + (i) * 4)
83 #define RV1106_PERICRU_GATE_CON_NUM 8
84
85 #define RV1106_NPUCRU_GATE_CON(i) (0x800 + (i) * 4)
86 #define RV1106_NPUCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
87 #define RV1106_NPUCRU_GATE_CON_NUM 2
88
89 #define RV1106_VENCCRU_GATE_CON(i) (0x800 + (i) * 4)
90 #define RV1106_VENCCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
91 #define RV1106_VENCCRU_GATE_CON_NUM 3
92
93 #define RV1106_VICRU_GATE_CON(i) (0x800 + (i) * 4)
94 #define RV1106_VICRU_CLKSEL_CON(i) (0x300 + (i) * 4)
95 #define RV1106_VICRU_GATE_CON_NUM 3
96
97 #define RV1106_VOCRU_GATE_CON(i) (0x800 + (i) * 4)
98 #define RV1106_VOCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
99 #define RV1106_VOCRU_GATE_CON_NUM 4
100
101 #define RV1106_CORECRU_GATE_CON(i) (0x800 + (i) * 4)
102 #define RV1106_COERCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
103 #define RV1106_CORECRU_GATE_CON_NUM 2
104
105 /* grf */
106 #define RV1106_PMUGRF_SOC_CON(i) ((i) * 4)
107 #define RV1106_PMUGRF_OS_REG(i) (0x200 + (i) * 4)
108
109 #define RV1106_PMUSGRF_SOC_CON(i) ((i) * 4)
110
111 #define RV1106_DDRGRF_CON(i) ((i) * 0x4)
112
113 /* pvmt */
114 #define RV1106_PVTM_CON(i) (0x4 + (i) * 4)
115 #define RV1106_PVTM_INTEN 0x70
116 #define RV1106_PVTM_INTSTS 0x74
117 #define RV1106_PVTM_STATUS(i) (0x80 + (i) * 4)
118
119 #define RV1106_PVTM_CALC_CNT 0x200
120
121 /* gpio */
122 #define RV1106_GPIO_SWPORT_DR_L 0x0000
123 #define RV1106_GPIO_SWPORT_DR_H 0x0004
124 #define RV1106_GPIO_SWPORT_DDR_L 0x0008
125 #define RV1106_GPIO_SWPORT_DDR_H 0x000c
126 #define RV1106_GPIO_INT_EN_L 0x0010
127 #define RV1106_GPIO_INT_EN_H 0x0014
128 #define RV1106_GPIO_INT_MASK_L 0x0018
129 #define RV1106_GPIO_INT_MASK_H 0x001c
130 #define RV1106_GPIO_INT_TYPE_L 0x0020
131 #define RV1106_GPIO_INT_TYPE_H 0x0024
132 #define RV1106_GPIO_INT_POLARITY_L 0x0028
133 #define RV1106_GPIO_INT_POLARITY_H 0x002c
134 #define RV1106_GPIO_INT_BOTHEDGE_L 0x0030
135 #define RV1106_GPIO_INT_BOTHEDGE_H 0x0034
136 #define RV1106_GPIO_DEBOUNCE_L 0x0038
137 #define RV1106_GPIO_DEBOUNCE_H 0x003c
138 #define RV1106_GPIO_DBCLK_DIV_EN_L 0x0040
139 #define RV1106_GPIO_DBCLK_DIV_EN_H 0x0044
140 #define RV1106_GPIO_DBCLK_DIV_CON 0x0048
141 #define RV1106_GPIO_INT_STATUS 0x0050
142 #define RV1106_GPIO_INT_RAWSTATUS 0x0058
143
144 /* pmu */
145 #define RV1106_PMU_VERSION 0x000
146 #define RV1106_PMU_PWR_CON 0x004
147 #define RV1106_PMU_GLB_POWER_STS 0x008
148 #define RV1106_PMU_INT_MASK_CON 0x00c
149 #define RV1106_PMU_WAKEUP_INT_CON 0x010
150 #define RV1106_PMU_WAKEUP_INT_ST 0x014
151 #define RV1106_PMU_PMIC_STABLE_CNT 0x024
152 #define RV1106_PMU_OSC_STABLE_CNT 0x028
153 #define RV1106_PMU_WAKEUP_RSTCLR_CNT 0x02c
154 #define RV1106_PMU_PLL_LOCK_CNT 0x030
155 #define RV1106_PMU_WAKEUP_TIMEOUT_CNT 0x048
156 #define RV1106_PMU_PWM_SWITCH_CNT 0x04c
157 #define RV1106_PMU_SCU_PWR_CON 0x080
158 #define RV1106_PMU_SCU_STS 0x084
159 #define RV1106_PMU_BIU_IDLE_CON 0x0b0
160 #define RV1106_PMU_BIU_IDLE_SFTCON 0x0c0
161 #define RV1106_PMU_BIU_IDLE_ACK 0x0d0
162 #define RV1106_PMU_BIU_IDLE_ST 0x0d8
163 #define RV1106_PMU_BIU_AUTO_CON 0x0e0
164 #define RV1106_PMU_DDR_PWR_CON 0x0f0
165 #define RV1106_PMU_DDR_PWR_SFTCON 0x0f4
166 #define RV1106_PMU_DDR_POWER_STS 0x0f8
167 #define RV1106_PMU_DDR_STS 0x0fC
168 #define RV1106_PMU_CRU_PWR_CON0 0x120
169 #define RV1106_PMU_CRU_PWR_CON1 0x140
170 #define RV1106_PMU_CRU_PWR_SFTCON 0x124
171 #define RV1106_PMU_CRU_POWER_STS 0x128
172 #define RV1106_PMU_PLLPD_CON 0x130
173 #define RV1106_PMU_PLLPD_SFTCON 0x134
174 #define RV1106_PMU_INFO_TX_CON 0x150
175 #define RV1106_PMU_SYS_REG(i) (0x1c0 + (i) * 4)
176
177 #define PMU_SUSPEND_MAGIC 0x02468ace
178 #define PMU_RESUME_MAGIC 0x13579bdf
179
180 #ifndef __ASSEMBLER__
181 extern unsigned long rkpm_bootdata_cpusp;
182 extern unsigned long rkpm_bootdata_cpu_code;
183 extern unsigned long rkpm_bootdata_l2ctlr_f;
184 extern unsigned long rkpm_bootdata_l2ctlr;
185 extern unsigned long rkpm_bootdata_ddr_code;
186 extern unsigned long rkpm_bootdata_ddr_data;
187 extern unsigned long rv1106_bootram_sz;
188
189 void rockchip_slp_cpu_resume(void);
190 void rv1106_rockchip_slp_cpu_resume(void);
191
192 #ifdef CONFIG_PM_SLEEP
193 void __init rockchip_suspend_init(void);
194 #else
rockchip_suspend_init(void)195 static inline void rockchip_suspend_init(void)
196 {
197 }
198 #endif
199
200 enum rv1106_pwr_con {
201 RV1106_PMU_PWRMODE_EN = 0,
202 RV1106_PMU_BUS_BYPASS = 4,
203 RV1106_PMU_DDR_BYPASS = 5,
204 RV1106_PMU_CRU_BYPASS = 7,
205 };
206
207 enum rv1106_int_mask_con {
208 RV1106_PMU_GLB_INT_MASK = 0,
209 };
210
211 enum rv1106_wakeup_init_con {
212 RV1106_PMU_WAKEUP_CPU_INT_EN = 0,
213 RV1106_PMU_WAKEUP_GPIO_INT_EN,
214 RV1106_PMU_WAKEUP_SDMMC_EN,
215 RV1106_PMU_WAKEUP_SDIO_EN,
216
217 RV1106_PMU_WAKEUP_USBDEV_EN,
218 RV1106_PMU_WAKEUP_TIMER_EN,
219 RV1106_PMU_WAKEUP_TIMEROUT_EN,
220 RV1106_PMU_WAKEUP_SFT_WAKEUP_CFG,
221 };
222
223 enum rv1106_scu_pwr_con {
224 RV1106_PMU_SCU_INT_MASK_ENA = 0,
225 RV1106_PMU_CPU_INT_MASK_ENA,
226 RV1106_PMU_STANDBYWFI_BYPASS,
227 };
228
229 enum rv1106_scu_sts {
230 RV1106_PMU_STANDBYWFI,
231 RV1106_PMU_STANDBYWFIL2,
232 };
233
234 enum rv1106_biu_idle_con {
235 RV1106_PMU_IDLE_REQ_MSCH = 0,
236 RV1106_PMU_IDLE_REQ_DDR,
237 RV1106_PMU_IDLE_REQ_NPU,
238 RV1106_PMU_IDLE_REQ_NPU_ACLK,
239
240 RV1106_PMU_IDLE_REQ_VI,
241 RV1106_PMU_IDLE_REQ_VO,
242 RV1106_PMU_IDLE_REQ_PERI,
243 RV1106_PMU_IDLE_REQ_CRU,
244
245 RV1106_PMU_IDLE_REQ_CPU,
246 RV1106_PMU_IDLE_REQ_VENC_COM,
247 RV1106_PMU_IDLE_REQ_VEPU,
248 };
249
250 enum rv1106_biu_auto_con {
251 RV1106_PMU_AUTO_IDLE_MSCH = 0,
252 RV1106_PMU_AUTO_IDLE_DDR,
253 RV1106_PMU_AUTO_IDLE_NPU,
254 RV1106_PMU_AUTO_IDLE_NPU_ACLK,
255
256 RV1106_PMU_AUTO_IDLE_VI,
257 RV1106_PMU_AUTO_IDLE_VO,
258 RV1106_PMU_AUTO_IDLE_PERI,
259 RV1106_PMU_AUTO_IDLE_CRU,
260
261 RV1106_PMU_AUTO_IDLE_CPU,
262 RV1106_PMU_AUTO_IDLE_VENC_COM,
263 RV1106_PMU_AUTO_IDLE_VEPU,
264 };
265
266 enum rv1106_ddr_pwr_con {
267 RV1106_PMU_DDR_SREF_C_ENA = 0,
268 RV1106_PMU_DDRIO_RET_ENA,
269 RV1106_PMU_DDRIO_EXIT_ENA,
270 RV1106_PMU_DDRCTL_C_AUTO_GATING_ENA,
271
272 RV1106_PMU_MSCH_AUTO_GATING_ENA = 5,
273 RV1106_PMU_DDR_SREF_A_ENA,
274 RV1106_PMU_DDRCTL_A_AUTO_GATING_ENA,
275 };
276
277 enum rv1106_cru_pwr_con0 {
278 RV1106_PMU_ALIVE_32K_ENA = 0,
279 RV1106_PMU_OSC_DIS_ENA,
280 RV1106_PMU_WAKEUP_RST_ENA,
281 RV1106_PMU_INPUT_CLAMP_ENA,
282
283 RV1106_PMU_ALIVE_OSC_ENA,
284 RV1106_PMU_POWER_OFF_ENA,
285 RV1106_PMU_PWM_SWITCH_ENA,
286 RV1106_PMU_GPIO_IOE_ENA,
287 RV1106_PMU_PWM_SWITCH_IOUT,
288 };
289
290 enum rv1106_cru_pwr_con1 {
291 RV1106_PMU_VI_CLK_SRC_GATE_ENA = 0,
292 RV1106_PMU_VO_CLK_SRC_GATE_ENA,
293 RV1106_PMU_VENC_CLK_SRC_GATE_ENA,
294 RV1106_PMU_NPU_CLK_SRC_GATE_ENA,
295
296 RV1106_PMU_DDR_CLK_SRC_CATE_ENA,
297 RV1106_PMU_PERI_CLK_SRC_GATE_ENA,
298 RV1106_PMU_CORE_CLK_SRC_GATE_ENA,
299 RV1106_PMU_CRU_CLK_SRC_GATE_ENA,
300 };
301
302 enum rv1106_pllpd_con {
303 RV1106_PMU_APLL_PD_ENA = 0,
304 RV1106_PMU_DPLL_PD_ENA,
305 RV1106_PMU_CPLL_PD_ENA,
306 RV1106_PMU_GPLL_PD_ENA,
307 };
308
309 enum rv1106_pllid {
310 RV1106_APLL_ID = 0,
311 RV1106_CPLL_ID,
312 RV1106_DPLL_ID,
313 RV1106_GPLL_ID,
314 };
315
316 enum pvtm_con0 {
317 PVTM_START = 0,
318 PVTM_OSC_EN = 1,
319 PVTM_OSC_SEL = 2,
320 PVTM_RND_SEED_EN = 5,
321 };
322
323 #endif
324 #endif /* __MACH_ROCKCHIP_RV1106_PM_H */
325