1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * 19 ******************************************************************************/ 20 #ifndef __INC_HAL8188EPHYREG_H__ 21 #define __INC_HAL8188EPHYREG_H__ 22 /*--------------------------Define Parameters-------------------------------*/ 23 // 24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF 25 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 27 // 3. RF register 0x00-2E 28 // 4. Bit Mask for BB/RF register 29 // 5. Other defintion for BB/RF R/W 30 // 31 32 33 // 34 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 35 // 1. Page1(0x100) 36 // 37 #define rPMAC_Reset 0x100 38 #define rPMAC_TxStart 0x104 39 #define rPMAC_TxLegacySIG 0x108 40 #define rPMAC_TxHTSIG1 0x10c 41 #define rPMAC_TxHTSIG2 0x110 42 #define rPMAC_PHYDebug 0x114 43 #define rPMAC_TxPacketNum 0x118 44 #define rPMAC_TxIdle 0x11c 45 #define rPMAC_TxMACHeader0 0x120 46 #define rPMAC_TxMACHeader1 0x124 47 #define rPMAC_TxMACHeader2 0x128 48 #define rPMAC_TxMACHeader3 0x12c 49 #define rPMAC_TxMACHeader4 0x130 50 #define rPMAC_TxMACHeader5 0x134 51 #define rPMAC_TxDataType 0x138 52 #define rPMAC_TxRandomSeed 0x13c 53 #define rPMAC_CCKPLCPPreamble 0x140 54 #define rPMAC_CCKPLCPHeader 0x144 55 #define rPMAC_CCKCRC16 0x148 56 #define rPMAC_OFDMRxCRC32OK 0x170 57 #define rPMAC_OFDMRxCRC32Er 0x174 58 #define rPMAC_OFDMRxParityEr 0x178 59 #define rPMAC_OFDMRxCRC8Er 0x17c 60 #define rPMAC_CCKCRxRC16Er 0x180 61 #define rPMAC_CCKCRxRC32Er 0x184 62 #define rPMAC_CCKCRxRC32OK 0x188 63 #define rPMAC_TxStatus 0x18c 64 65 // 66 // 2. Page2(0x200) 67 // 68 // The following two definition are only used for USB interface. 69 #define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. 70 #define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. 71 72 // 73 // 3. Page8(0x800) 74 // 75 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? 76 77 #define rFPGA0_TxInfo 0x804 // Status report?? 78 #define rFPGA0_PSDFunction 0x808 79 80 #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? 81 82 #define rFPGA0_RFTiming1 0x810 // Useless now 83 #define rFPGA0_RFTiming2 0x814 84 85 #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register 86 #define rFPGA0_XA_HSSIParameter2 0x824 87 #define rFPGA0_XB_HSSIParameter1 0x828 88 #define rFPGA0_XB_HSSIParameter2 0x82c 89 90 #define rFPGA0_XA_LSSIParameter 0x840 91 #define rFPGA0_XB_LSSIParameter 0x844 92 93 #define rFPGA0_RFWakeUpParameter 0x850 // Useless now 94 #define rFPGA0_RFSleepUpParameter 0x854 95 96 #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch 97 #define rFPGA0_XCD_SwitchControl 0x85c 98 99 #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch 100 #define rFPGA0_XB_RFInterfaceOE 0x864 101 #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control 102 #define rFPGA0_XCD_RFInterfaceSW 0x874 103 104 #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter 105 #define rFPGA0_XCD_RFParameter 0x87c 106 107 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? 108 #define rFPGA0_AnalogParameter2 0x884 109 #define rFPGA0_AnalogParameter3 0x888 110 #define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy 111 #define rFPGA0_AnalogParameter4 0x88c 112 113 #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback 114 #define rFPGA0_XB_LSSIReadBack 0x8a4 115 #define rFPGA0_XC_LSSIReadBack 0x8a8 116 #define rFPGA0_XD_LSSIReadBack 0x8ac 117 118 #define rFPGA0_PSDReport 0x8b4 // Useless now 119 #define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback 120 #define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback 121 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value 122 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now 123 124 // 125 // 4. Page9(0x900) 126 // 127 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? 128 129 #define rFPGA1_TxBlock 0x904 // Useless now 130 #define rFPGA1_DebugSelect 0x908 // Useless now 131 #define rFPGA1_TxInfo 0x90c // Useless now // Status report?? 132 133 // 134 // 5. PageA(0xA00) 135 // 136 // Set Control channel to upper or lower. These settings are required only for 40MHz 137 #define rCCK0_System 0xa00 138 139 #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI 140 #define rCCK0_CCA 0xa08 // Disable init gain now // Init gain 141 142 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series 143 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC 144 145 #define rCCK0_RxHP 0xa14 146 147 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold 148 #define rCCK0_DSPParameter2 0xa1c //SQ threshold 149 150 #define rCCK0_TxFilter1 0xa20 151 #define rCCK0_TxFilter2 0xa24 152 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 153 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report 154 #define rCCK0_TRSSIReport 0xa50 155 #define rCCK0_RxReport 0xa54 //0xa57 156 #define rCCK0_FACounterLower 0xa5c //0xa5b 157 #define rCCK0_FACounterUpper 0xa58 //0xa5c 158 159 // 160 // PageB(0xB00) 161 // 162 #define rPdp_AntA 0xb00 163 #define rPdp_AntA_4 0xb04 164 #define rConfig_Pmpd_AntA 0xb28 165 #define rConfig_ram64x16 0xb2c 166 #define rConfig_AntA 0xb68 167 #define rConfig_AntB 0xb6c 168 #define rPdp_AntB 0xb70 169 #define rPdp_AntB_4 0xb74 170 #define rConfig_Pmpd_AntB 0xb98 171 #define rAPK 0xbd8 172 173 174 175 // 176 // 6. PageC(0xC00) 177 // 178 #define rOFDM0_LSTF 0xc00 179 180 #define rOFDM0_TRxPathEnable 0xc04 181 #define rOFDM0_TRMuxPar 0xc08 182 #define rOFDM0_TRSWIsolation 0xc0c 183 184 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter 185 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix 186 #define rOFDM0_XBRxAFE 0xc18 187 #define rOFDM0_XBRxIQImbalance 0xc1c 188 #define rOFDM0_XCRxAFE 0xc20 189 #define rOFDM0_XCRxIQImbalance 0xc24 190 #define rOFDM0_XDRxAFE 0xc28 191 #define rOFDM0_XDRxIQImbalance 0xc2c 192 193 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain 194 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. 195 #define rOFDM0_RxDetector3 0xc38 //Frame Sync. 196 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI 197 198 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path 199 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC 200 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold 201 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA 202 203 #define rOFDM0_XAAGCCore1 0xc50 // DIG 204 #define rOFDM0_XAAGCCore2 0xc54 205 #define rOFDM0_XBAGCCore1 0xc58 206 #define rOFDM0_XBAGCCore2 0xc5c 207 #define rOFDM0_XCAGCCore1 0xc60 208 #define rOFDM0_XCAGCCore2 0xc64 209 #define rOFDM0_XDAGCCore1 0xc68 210 #define rOFDM0_XDAGCCore2 0xc6c 211 212 #define rOFDM0_AGCParameter1 0xc70 213 #define rOFDM0_AGCParameter2 0xc74 214 #define rOFDM0_AGCRSSITable 0xc78 215 #define rOFDM0_HTSTFAGC 0xc7c 216 217 #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG 218 #define rOFDM0_XATxAFE 0xc84 219 #define rOFDM0_XBTxIQImbalance 0xc88 220 #define rOFDM0_XBTxAFE 0xc8c 221 #define rOFDM0_XCTxIQImbalance 0xc90 222 #define rOFDM0_XCTxAFE 0xc94 223 #define rOFDM0_XDTxIQImbalance 0xc98 224 #define rOFDM0_XDTxAFE 0xc9c 225 226 #define rOFDM0_RxIQExtAnta 0xca0 227 #define rOFDM0_TxCoeff1 0xca4 228 #define rOFDM0_TxCoeff2 0xca8 229 #define rOFDM0_TxCoeff3 0xcac 230 #define rOFDM0_TxCoeff4 0xcb0 231 #define rOFDM0_TxCoeff5 0xcb4 232 #define rOFDM0_TxCoeff6 0xcb8 233 #define rOFDM0_RxHPParameter 0xce0 234 #define rOFDM0_TxPseudoNoiseWgt 0xce4 235 #define rOFDM0_FrameSync 0xcf0 236 #define rOFDM0_DFSReport 0xcf4 237 238 239 // 240 // 7. PageD(0xD00) 241 // 242 #define rOFDM1_LSTF 0xd00 243 #define rOFDM1_TRxPathEnable 0xd04 244 245 #define rOFDM1_CFO 0xd08 // No setting now 246 #define rOFDM1_CSI1 0xd10 247 #define rOFDM1_SBD 0xd14 248 #define rOFDM1_CSI2 0xd18 249 #define rOFDM1_CFOTracking 0xd2c 250 #define rOFDM1_TRxMesaure1 0xd34 251 #define rOFDM1_IntfDet 0xd3c 252 #define rOFDM1_csi_fix_mask1 0xd40 253 #define rOFDM1_csi_fix_mask2 0xd44 254 #define rOFDM1_PseudoNoiseStateAB 0xd50 255 #define rOFDM1_PseudoNoiseStateCD 0xd54 256 #define rOFDM1_RxPseudoNoiseWgt 0xd58 257 258 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail 259 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail 260 #define rOFDM_PHYCounter3 0xda8 //MCS not support 261 262 #define rOFDM_ShortCFOAB 0xdac // No setting now 263 #define rOFDM_ShortCFOCD 0xdb0 264 #define rOFDM_LongCFOAB 0xdb4 265 #define rOFDM_LongCFOCD 0xdb8 266 #define rOFDM_TailCFOAB 0xdbc 267 #define rOFDM_TailCFOCD 0xdc0 268 #define rOFDM_PWMeasure1 0xdc4 269 #define rOFDM_PWMeasure2 0xdc8 270 #define rOFDM_BWReport 0xdcc 271 #define rOFDM_AGCReport 0xdd0 272 #define rOFDM_RxSNR 0xdd4 273 #define rOFDM_RxEVMCSI 0xdd8 274 #define rOFDM_SIGReport 0xddc 275 276 277 // 278 // 8. PageE(0xE00) 279 // 280 #define rTxAGC_A_Rate18_06 0xe00 281 #define rTxAGC_A_Rate54_24 0xe04 282 #define rTxAGC_A_CCK1_Mcs32 0xe08 283 #define rTxAGC_A_Mcs03_Mcs00 0xe10 284 #define rTxAGC_A_Mcs07_Mcs04 0xe14 285 #define rTxAGC_A_Mcs11_Mcs08 0xe18 286 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 287 288 #define rTxAGC_B_Rate18_06 0x830 289 #define rTxAGC_B_Rate54_24 0x834 290 #define rTxAGC_B_CCK1_55_Mcs32 0x838 291 #define rTxAGC_B_Mcs03_Mcs00 0x83c 292 #define rTxAGC_B_Mcs07_Mcs04 0x848 293 #define rTxAGC_B_Mcs11_Mcs08 0x84c 294 #define rTxAGC_B_Mcs15_Mcs12 0x868 295 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 296 297 #define rFPGA0_IQK 0xe28 298 #define rTx_IQK_Tone_A 0xe30 299 #define rRx_IQK_Tone_A 0xe34 300 #define rTx_IQK_PI_A 0xe38 301 #define rRx_IQK_PI_A 0xe3c 302 303 #define rTx_IQK 0xe40 304 #define rRx_IQK 0xe44 305 #define rIQK_AGC_Pts 0xe48 306 #define rIQK_AGC_Rsp 0xe4c 307 #define rTx_IQK_Tone_B 0xe50 308 #define rRx_IQK_Tone_B 0xe54 309 #define rTx_IQK_PI_B 0xe58 310 #define rRx_IQK_PI_B 0xe5c 311 #define rIQK_AGC_Cont 0xe60 312 313 #define rBlue_Tooth 0xe6c 314 #define rRx_Wait_CCA 0xe70 315 #define rTx_CCK_RFON 0xe74 316 #define rTx_CCK_BBON 0xe78 317 #define rTx_OFDM_RFON 0xe7c 318 #define rTx_OFDM_BBON 0xe80 319 #define rTx_To_Rx 0xe84 320 #define rTx_To_Tx 0xe88 321 #define rRx_CCK 0xe8c 322 323 #define rTx_Power_Before_IQK_A 0xe94 324 #define rTx_Power_After_IQK_A 0xe9c 325 326 #define rRx_Power_Before_IQK_A 0xea0 327 #define rRx_Power_Before_IQK_A_2 0xea4 328 #define rRx_Power_After_IQK_A 0xea8 329 #define rRx_Power_After_IQK_A_2 0xeac 330 331 #define rTx_Power_Before_IQK_B 0xeb4 332 #define rTx_Power_After_IQK_B 0xebc 333 334 #define rRx_Power_Before_IQK_B 0xec0 335 #define rRx_Power_Before_IQK_B_2 0xec4 336 #define rRx_Power_After_IQK_B 0xec8 337 #define rRx_Power_After_IQK_B_2 0xecc 338 339 #define rRx_OFDM 0xed0 340 #define rRx_Wait_RIFS 0xed4 341 #define rRx_TO_Rx 0xed8 342 #define rStandby 0xedc 343 #define rSleep 0xee0 344 #define rPMPD_ANAEN 0xeec 345 346 // 347 // 7. RF Register 0x00-0x2E (RF 8256) 348 // RF-0222D 0x00-3F 349 // 350 //Zebra1 351 #define rZebra1_HSSIEnable 0x0 // Useless now 352 #define rZebra1_TRxEnable1 0x1 353 #define rZebra1_TRxEnable2 0x2 354 #define rZebra1_AGC 0x4 355 #define rZebra1_ChargePump 0x5 356 #define rZebra1_Channel 0x7 // RF channel switch 357 358 //#endif 359 #define rZebra1_TxGain 0x8 // Useless now 360 #define rZebra1_TxLPF 0x9 361 #define rZebra1_RxLPF 0xb 362 #define rZebra1_RxHPFCorner 0xc 363 364 //Zebra4 365 #define rGlobalCtrl 0 // Useless now 366 #define rRTL8256_TxLPF 19 367 #define rRTL8256_RxLPF 11 368 369 //RTL8258 370 #define rRTL8258_TxLPF 0x11 // Useless now 371 #define rRTL8258_RxLPF 0x13 372 #define rRTL8258_RSSILPF 0xa 373 374 // 375 // RL6052 Register definition 376 // 377 #define RF_AC 0x00 // 378 379 #define RF_IQADJ_G1 0x01 // 380 #define RF_IQADJ_G2 0x02 // 381 382 #define RF_POW_TRSW 0x05 // 383 384 #define RF_GAIN_RX 0x06 // 385 #define RF_GAIN_TX 0x07 // 386 387 #define RF_TXM_IDAC 0x08 // 388 #define RF_IPA_G 0x09 // 389 #define RF_TXBIAS_G 0x0A 390 #define RF_TXPA_AG 0x0B 391 #define RF_IPA_A 0x0C // 392 #define RF_TXBIAS_A 0x0D 393 #define RF_BS_PA_APSET_G9_G11 0x0E 394 #define RF_BS_IQGEN 0x0F // 395 396 #define RF_MODE1 0x10 // 397 #define RF_MODE2 0x11 // 398 399 #define RF_RX_AGC_HP 0x12 // 400 #define RF_TX_AGC 0x13 // 401 #define RF_BIAS 0x14 // 402 #define RF_IPA 0x15 // 403 #define RF_TXBIAS 0x16 404 #define RF_POW_ABILITY 0x17 // 405 #define RF_CHNLBW 0x18 // RF channel and BW switch 406 #define RF_TOP 0x19 // 407 408 #define RF_RX_G1 0x1A // 409 #define RF_RX_G2 0x1B // 410 411 #define RF_RX_BB2 0x1C // 412 #define RF_RX_BB1 0x1D // 413 414 #define RF_RCK1 0x1E // 415 #define RF_RCK2 0x1F // 416 417 #define RF_TX_G1 0x20 // 418 #define RF_TX_G2 0x21 // 419 #define RF_TX_G3 0x22 // 420 421 #define RF_TX_BB1 0x23 // 422 423 #define RF_T_METER_88E 0x42 // 424 #define RF_T_METER 0x24 // 425 426 #define RF_SYN_G1 0x25 // RF TX Power control 427 #define RF_SYN_G2 0x26 // RF TX Power control 428 #define RF_SYN_G3 0x27 // RF TX Power control 429 #define RF_SYN_G4 0x28 // RF TX Power control 430 #define RF_SYN_G5 0x29 // RF TX Power control 431 #define RF_SYN_G6 0x2A // RF TX Power control 432 #define RF_SYN_G7 0x2B // RF TX Power control 433 #define RF_SYN_G8 0x2C // RF TX Power control 434 435 #define RF_RCK_OS 0x30 // RF TX PA control 436 #define RF_TXPA_G1 0x31 // RF TX PA control 437 #define RF_TXPA_G2 0x32 // RF TX PA control 438 #define RF_TXPA_G3 0x33 // RF TX PA control 439 #define RF_TX_BIAS_A 0x35 440 #define RF_TX_BIAS_D 0x36 441 #define RF_LOBF_9 0x38 442 #define RF_RXRF_A3 0x3C // 443 #define RF_TRSW 0x3F 444 445 #define RF_TXRF_A2 0x41 446 #define RF_TXPA_G4 0x46 447 #define RF_TXPA_A4 0x4B 448 #define RF_0x52 0x52 449 #define RF_WE_LUT 0xEF 450 451 452 // 453 //Bit Mask 454 // 455 // 1. Page1(0x100) 456 #define bBBResetB 0x100 // Useless now? 457 #define bGlobalResetB 0x200 458 #define bOFDMTxStart 0x4 459 #define bCCKTxStart 0x8 460 #define bCRC32Debug 0x100 461 #define bPMACLoopback 0x10 462 #define bTxLSIG 0xffffff 463 #define bOFDMTxRate 0xf 464 #define bOFDMTxReserved 0x10 465 #define bOFDMTxLength 0x1ffe0 466 #define bOFDMTxParity 0x20000 467 #define bTxHTSIG1 0xffffff 468 #define bTxHTMCSRate 0x7f 469 #define bTxHTBW 0x80 470 #define bTxHTLength 0xffff00 471 #define bTxHTSIG2 0xffffff 472 #define bTxHTSmoothing 0x1 473 #define bTxHTSounding 0x2 474 #define bTxHTReserved 0x4 475 #define bTxHTAggreation 0x8 476 #define bTxHTSTBC 0x30 477 #define bTxHTAdvanceCoding 0x40 478 #define bTxHTShortGI 0x80 479 #define bTxHTNumberHT_LTF 0x300 480 #define bTxHTCRC8 0x3fc00 481 #define bCounterReset 0x10000 482 #define bNumOfOFDMTx 0xffff 483 #define bNumOfCCKTx 0xffff0000 484 #define bTxIdleInterval 0xffff 485 #define bOFDMService 0xffff0000 486 #define bTxMACHeader 0xffffffff 487 #define bTxDataInit 0xff 488 #define bTxHTMode 0x100 489 #define bTxDataType 0x30000 490 #define bTxRandomSeed 0xffffffff 491 #define bCCKTxPreamble 0x1 492 #define bCCKTxSFD 0xffff0000 493 #define bCCKTxSIG 0xff 494 #define bCCKTxService 0xff00 495 #define bCCKLengthExt 0x8000 496 #define bCCKTxLength 0xffff0000 497 #define bCCKTxCRC16 0xffff 498 #define bCCKTxStatus 0x1 499 #define bOFDMTxStatus 0x2 500 501 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 502 503 // 2. Page8(0x800) 504 #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD 505 #define bJapanMode 0x2 506 #define bCCKTxSC 0x30 507 #define bCCKEn 0x1000000 508 #define bOFDMEn 0x2000000 509 510 #define bOFDMRxADCPhase 0x10000 // Useless now 511 #define bOFDMTxDACPhase 0x40000 512 #define bXATxAGC 0x3f 513 514 #define bAntennaSelect 0x0300 515 516 #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage 517 #define bXCTxAGC 0xf000 518 #define bXDTxAGC 0xf0000 519 520 #define bPAStart 0xf0000000 // Useless now 521 #define bTRStart 0x00f00000 522 #define bRFStart 0x0000f000 523 #define bBBStart 0x000000f0 524 #define bBBCCKStart 0x0000000f 525 #define bPAEnd 0xf //Reg0x814 526 #define bTREnd 0x0f000000 527 #define bRFEnd 0x000f0000 528 #define bCCAMask 0x000000f0 //T2R 529 #define bR2RCCAMask 0x00000f00 530 #define bHSSI_R2TDelay 0xf8000000 531 #define bHSSI_T2RDelay 0xf80000 532 #define bContTxHSSI 0x400 //chane gain at continue Tx 533 #define bIGFromCCK 0x200 534 #define bAGCAddress 0x3f 535 #define bRxHPTx 0x7000 536 #define bRxHPT2R 0x38000 537 #define bRxHPCCKIni 0xc0000 538 #define bAGCTxCode 0xc00000 539 #define bAGCRxCode 0x300000 540 541 #define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 542 #define b3WireAddressLength 0x400 543 544 #define b3WireRFPowerDown 0x1 // Useless now 545 //#define bHWSISelect 0x8 546 #define b5GPAPEPolarity 0x40000000 547 #define b2GPAPEPolarity 0x80000000 548 #define bRFSW_TxDefaultAnt 0x3 549 #define bRFSW_TxOptionAnt 0x30 550 #define bRFSW_RxDefaultAnt 0x300 551 #define bRFSW_RxOptionAnt 0x3000 552 #define bRFSI_3WireData 0x1 553 #define bRFSI_3WireClock 0x2 554 #define bRFSI_3WireLoad 0x4 555 #define bRFSI_3WireRW 0x8 556 #define bRFSI_3Wire 0xf 557 558 #define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW 559 560 #define bRFSI_TRSW 0x20 // Useless now 561 #define bRFSI_TRSWB 0x40 562 #define bRFSI_ANTSW 0x100 563 #define bRFSI_ANTSWB 0x200 564 #define bRFSI_PAPE 0x400 565 #define bRFSI_PAPE5G 0x800 566 #define bBandSelect 0x1 567 #define bHTSIG2_GI 0x80 568 #define bHTSIG2_Smoothing 0x01 569 #define bHTSIG2_Sounding 0x02 570 #define bHTSIG2_Aggreaton 0x08 571 #define bHTSIG2_STBC 0x30 572 #define bHTSIG2_AdvCoding 0x40 573 #define bHTSIG2_NumOfHTLTF 0x300 574 #define bHTSIG2_CRC8 0x3fc 575 #define bHTSIG1_MCS 0x7f 576 #define bHTSIG1_BandWidth 0x80 577 #define bHTSIG1_HTLength 0xffff 578 #define bLSIG_Rate 0xf 579 #define bLSIG_Reserved 0x10 580 #define bLSIG_Length 0x1fffe 581 #define bLSIG_Parity 0x20 582 #define bCCKRxPhase 0x4 583 584 #define bLSSIReadAddress 0x7f800000 // T65 RF 585 586 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal 587 588 #define bLSSIReadBackData 0xfffff // T65 RF 589 590 #define bLSSIReadOKFlag 0x1000 // Useless now 591 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz 592 #define bRegulator0Standby 0x1 593 #define bRegulatorPLLStandby 0x2 594 #define bRegulator1Standby 0x4 595 #define bPLLPowerUp 0x8 596 #define bDPLLPowerUp 0x10 597 #define bDA10PowerUp 0x20 598 #define bAD7PowerUp 0x200 599 #define bDA6PowerUp 0x2000 600 #define bXtalPowerUp 0x4000 601 #define b40MDClkPowerUP 0x8000 602 #define bDA6DebugMode 0x20000 603 #define bDA6Swing 0x380000 604 605 #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ 606 607 #define b80MClkDelay 0x18000000 // Useless 608 #define bAFEWatchDogEnable 0x20000000 609 610 #define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap 611 #define bXtalCap23 0x3 612 #define bXtalCap92x 0x0f000000 613 #define bXtalCap 0x0f000000 614 615 #define bIntDifClkEnable 0x400 // Useless 616 #define bExtSigClkEnable 0x800 617 #define bBandgapMbiasPowerUp 0x10000 618 #define bAD11SHGain 0xc0000 619 #define bAD11InputRange 0x700000 620 #define bAD11OPCurrent 0x3800000 621 #define bIPathLoopback 0x4000000 622 #define bQPathLoopback 0x8000000 623 #define bAFELoopback 0x10000000 624 #define bDA10Swing 0x7e0 625 #define bDA10Reverse 0x800 626 #define bDAClkSource 0x1000 627 #define bAD7InputRange 0x6000 628 #define bAD7Gain 0x38000 629 #define bAD7OutputCMMode 0x40000 630 #define bAD7InputCMMode 0x380000 631 #define bAD7Current 0xc00000 632 #define bRegulatorAdjust 0x7000000 633 #define bAD11PowerUpAtTx 0x1 634 #define bDA10PSAtTx 0x10 635 #define bAD11PowerUpAtRx 0x100 636 #define bDA10PSAtRx 0x1000 637 #define bCCKRxAGCFormat 0x200 638 #define bPSDFFTSamplepPoint 0xc000 639 #define bPSDAverageNum 0x3000 640 #define bIQPathControl 0xc00 641 #define bPSDFreq 0x3ff 642 #define bPSDAntennaPath 0x30 643 #define bPSDIQSwitch 0x40 644 #define bPSDRxTrigger 0x400000 645 #define bPSDTxTrigger 0x80000000 646 #define bPSDSineToneScale 0x7f000000 647 #define bPSDReport 0xffff 648 649 // 3. Page9(0x900) 650 #define bOFDMTxSC 0x30000000 // Useless 651 #define bCCKTxOn 0x1 652 #define bOFDMTxOn 0x2 653 #define bDebugPage 0xfff //reset debug page and also HWord, LWord 654 #define bDebugItem 0xff //reset debug page and LWord 655 #define bAntL 0x10 656 #define bAntNonHT 0x100 657 #define bAntHT1 0x1000 658 #define bAntHT2 0x10000 659 #define bAntHT1S1 0x100000 660 #define bAntNonHTS1 0x1000000 661 662 // 4. PageA(0xA00) 663 #define bCCKBBMode 0x3 // Useless 664 #define bCCKTxPowerSaving 0x80 665 #define bCCKRxPowerSaving 0x40 666 667 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch 668 669 #define bCCKScramble 0x8 // Useless 670 #define bCCKAntDiversity 0x8000 671 #define bCCKCarrierRecovery 0x4000 672 #define bCCKTxRate 0x3000 673 #define bCCKDCCancel 0x0800 674 #define bCCKISICancel 0x0400 675 #define bCCKMatchFilter 0x0200 676 #define bCCKEqualizer 0x0100 677 #define bCCKPreambleDetect 0x800000 678 #define bCCKFastFalseCCA 0x400000 679 #define bCCKChEstStart 0x300000 680 #define bCCKCCACount 0x080000 681 #define bCCKcs_lim 0x070000 682 #define bCCKBistMode 0x80000000 683 #define bCCKCCAMask 0x40000000 684 #define bCCKTxDACPhase 0x4 685 #define bCCKRxADCPhase 0x20000000 //r_rx_clk 686 #define bCCKr_cp_mode0 0x0100 687 #define bCCKTxDCOffset 0xf0 688 #define bCCKRxDCOffset 0xf 689 #define bCCKCCAMode 0xc000 690 #define bCCKFalseCS_lim 0x3f00 691 #define bCCKCS_ratio 0xc00000 692 #define bCCKCorgBit_sel 0x300000 693 #define bCCKPD_lim 0x0f0000 694 #define bCCKNewCCA 0x80000000 695 #define bCCKRxHPofIG 0x8000 696 #define bCCKRxIG 0x7f00 697 #define bCCKLNAPolarity 0x800000 698 #define bCCKRx1stGain 0x7f0000 699 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity 700 #define bCCKRxAGCSatLevel 0x1f000000 701 #define bCCKRxAGCSatCount 0xe0 702 #define bCCKRxRFSettle 0x1f //AGCsamp_dly 703 #define bCCKFixedRxAGC 0x8000 704 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 705 #define bCCKAntennaPolarity 0x2000 706 #define bCCKTxFilterType 0x0c00 707 #define bCCKRxAGCReportType 0x0300 708 #define bCCKRxDAGCEn 0x80000000 709 #define bCCKRxDAGCPeriod 0x20000000 710 #define bCCKRxDAGCSatLevel 0x1f000000 711 #define bCCKTimingRecovery 0x800000 712 #define bCCKTxC0 0x3f0000 713 #define bCCKTxC1 0x3f000000 714 #define bCCKTxC2 0x3f 715 #define bCCKTxC3 0x3f00 716 #define bCCKTxC4 0x3f0000 717 #define bCCKTxC5 0x3f000000 718 #define bCCKTxC6 0x3f 719 #define bCCKTxC7 0x3f00 720 #define bCCKDebugPort 0xff0000 721 #define bCCKDACDebug 0x0f000000 722 #define bCCKFalseAlarmEnable 0x8000 723 #define bCCKFalseAlarmRead 0x4000 724 #define bCCKTRSSI 0x7f 725 #define bCCKRxAGCReport 0xfe 726 #define bCCKRxReport_AntSel 0x80000000 727 #define bCCKRxReport_MFOff 0x40000000 728 #define bCCKRxRxReport_SQLoss 0x20000000 729 #define bCCKRxReport_Pktloss 0x10000000 730 #define bCCKRxReport_Lockedbit 0x08000000 731 #define bCCKRxReport_RateError 0x04000000 732 #define bCCKRxReport_RxRate 0x03000000 733 #define bCCKRxFACounterLower 0xff 734 #define bCCKRxFACounterUpper 0xff000000 735 #define bCCKRxHPAGCStart 0xe000 736 #define bCCKRxHPAGCFinal 0x1c00 737 #define bCCKRxFalseAlarmEnable 0x8000 738 #define bCCKFACounterFreeze 0x4000 739 #define bCCKTxPathSel 0x10000000 740 #define bCCKDefaultRxPath 0xc000000 741 #define bCCKOptionRxPath 0x3000000 742 743 // 5. PageC(0xC00) 744 #define bNumOfSTF 0x3 // Useless 745 #define bShift_L 0xc0 746 #define bGI_TH 0xc 747 #define bRxPathA 0x1 748 #define bRxPathB 0x2 749 #define bRxPathC 0x4 750 #define bRxPathD 0x8 751 #define bTxPathA 0x1 752 #define bTxPathB 0x2 753 #define bTxPathC 0x4 754 #define bTxPathD 0x8 755 #define bTRSSIFreq 0x200 756 #define bADCBackoff 0x3000 757 #define bDFIRBackoff 0xc000 758 #define bTRSSILatchPhase 0x10000 759 #define bRxIDCOffset 0xff 760 #define bRxQDCOffset 0xff00 761 #define bRxDFIRMode 0x1800000 762 #define bRxDCNFType 0xe000000 763 #define bRXIQImb_A 0x3ff 764 #define bRXIQImb_B 0xfc00 765 #define bRXIQImb_C 0x3f0000 766 #define bRXIQImb_D 0xffc00000 767 #define bDC_dc_Notch 0x60000 768 #define bRxNBINotch 0x1f000000 769 #define bPD_TH 0xf 770 #define bPD_TH_Opt2 0xc000 771 #define bPWED_TH 0x700 772 #define bIfMF_Win_L 0x800 773 #define bPD_Option 0x1000 774 #define bMF_Win_L 0xe000 775 #define bBW_Search_L 0x30000 776 #define bwin_enh_L 0xc0000 777 #define bBW_TH 0x700000 778 #define bED_TH2 0x3800000 779 #define bBW_option 0x4000000 780 #define bRatio_TH 0x18000000 781 #define bWindow_L 0xe0000000 782 #define bSBD_Option 0x1 783 #define bFrame_TH 0x1c 784 #define bFS_Option 0x60 785 #define bDC_Slope_check 0x80 786 #define bFGuard_Counter_DC_L 0xe00 787 #define bFrame_Weight_Short 0x7000 788 #define bSub_Tune 0xe00000 789 #define bFrame_DC_Length 0xe000000 790 #define bSBD_start_offset 0x30000000 791 #define bFrame_TH_2 0x7 792 #define bFrame_GI2_TH 0x38 793 #define bGI2_Sync_en 0x40 794 #define bSarch_Short_Early 0x300 795 #define bSarch_Short_Late 0xc00 796 #define bSarch_GI2_Late 0x70000 797 #define bCFOAntSum 0x1 798 #define bCFOAcc 0x2 799 #define bCFOStartOffset 0xc 800 #define bCFOLookBack 0x70 801 #define bCFOSumWeight 0x80 802 #define bDAGCEnable 0x10000 803 #define bTXIQImb_A 0x3ff 804 #define bTXIQImb_B 0xfc00 805 #define bTXIQImb_C 0x3f0000 806 #define bTXIQImb_D 0xffc00000 807 #define bTxIDCOffset 0xff 808 #define bTxQDCOffset 0xff00 809 #define bTxDFIRMode 0x10000 810 #define bTxPesudoNoiseOn 0x4000000 811 #define bTxPesudoNoise_A 0xff 812 #define bTxPesudoNoise_B 0xff00 813 #define bTxPesudoNoise_C 0xff0000 814 #define bTxPesudoNoise_D 0xff000000 815 #define bCCADropOption 0x20000 816 #define bCCADropThres 0xfff00000 817 #define bEDCCA_H 0xf 818 #define bEDCCA_L 0xf0 819 #define bLambda_ED 0x300 820 #define bRxInitialGain 0x7f 821 #define bRxAntDivEn 0x80 822 #define bRxAGCAddressForLNA 0x7f00 823 #define bRxHighPowerFlow 0x8000 824 #define bRxAGCFreezeThres 0xc0000 825 #define bRxFreezeStep_AGC1 0x300000 826 #define bRxFreezeStep_AGC2 0xc00000 827 #define bRxFreezeStep_AGC3 0x3000000 828 #define bRxFreezeStep_AGC0 0xc000000 829 #define bRxRssi_Cmp_En 0x10000000 830 #define bRxQuickAGCEn 0x20000000 831 #define bRxAGCFreezeThresMode 0x40000000 832 #define bRxOverFlowCheckType 0x80000000 833 #define bRxAGCShift 0x7f 834 #define bTRSW_Tri_Only 0x80 835 #define bPowerThres 0x300 836 #define bRxAGCEn 0x1 837 #define bRxAGCTogetherEn 0x2 838 #define bRxAGCMin 0x4 839 #define bRxHP_Ini 0x7 840 #define bRxHP_TRLNA 0x70 841 #define bRxHP_RSSI 0x700 842 #define bRxHP_BBP1 0x7000 843 #define bRxHP_BBP2 0x70000 844 #define bRxHP_BBP3 0x700000 845 #define bRSSI_H 0x7f0000 //the threshold for high power 846 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity 847 #define bRxSettle_TRSW 0x7 848 #define bRxSettle_LNA 0x38 849 #define bRxSettle_RSSI 0x1c0 850 #define bRxSettle_BBP 0xe00 851 #define bRxSettle_RxHP 0x7000 852 #define bRxSettle_AntSW_RSSI 0x38000 853 #define bRxSettle_AntSW 0xc0000 854 #define bRxProcessTime_DAGC 0x300000 855 #define bRxSettle_HSSI 0x400000 856 #define bRxProcessTime_BBPPW 0x800000 857 #define bRxAntennaPowerShift 0x3000000 858 #define bRSSITableSelect 0xc000000 859 #define bRxHP_Final 0x7000000 860 #define bRxHTSettle_BBP 0x7 861 #define bRxHTSettle_HSSI 0x8 862 #define bRxHTSettle_RxHP 0x70 863 #define bRxHTSettle_BBPPW 0x80 864 #define bRxHTSettle_Idle 0x300 865 #define bRxHTSettle_Reserved 0x1c00 866 #define bRxHTRxHPEn 0x8000 867 #define bRxHTAGCFreezeThres 0x30000 868 #define bRxHTAGCTogetherEn 0x40000 869 #define bRxHTAGCMin 0x80000 870 #define bRxHTAGCEn 0x100000 871 #define bRxHTDAGCEn 0x200000 872 #define bRxHTRxHP_BBP 0x1c00000 873 #define bRxHTRxHP_Final 0xe0000000 874 #define bRxPWRatioTH 0x3 875 #define bRxPWRatioEn 0x4 876 #define bRxMFHold 0x3800 877 #define bRxPD_Delay_TH1 0x38 878 #define bRxPD_Delay_TH2 0x1c0 879 #define bRxPD_DC_COUNT_MAX 0x600 880 //#define bRxMF_Hold 0x3800 881 #define bRxPD_Delay_TH 0x8000 882 #define bRxProcess_Delay 0xf0000 883 #define bRxSearchrange_GI2_Early 0x700000 884 #define bRxFrame_Guard_Counter_L 0x3800000 885 #define bRxSGI_Guard_L 0xc000000 886 #define bRxSGI_Search_L 0x30000000 887 #define bRxSGI_TH 0xc0000000 888 #define bDFSCnt0 0xff 889 #define bDFSCnt1 0xff00 890 #define bDFSFlag 0xf0000 891 #define bMFWeightSum 0x300000 892 #define bMinIdxTH 0x7f000000 893 #define bDAFormat 0x40000 894 #define bTxChEmuEnable 0x01000000 895 #define bTRSWIsolation_A 0x7f 896 #define bTRSWIsolation_B 0x7f00 897 #define bTRSWIsolation_C 0x7f0000 898 #define bTRSWIsolation_D 0x7f000000 899 #define bExtLNAGain 0x7c00 900 901 // 6. PageE(0xE00) 902 #define bSTBCEn 0x4 // Useless 903 #define bAntennaMapping 0x10 904 #define bNss 0x20 905 #define bCFOAntSumD 0x200 906 #define bPHYCounterReset 0x8000000 907 #define bCFOReportGet 0x4000000 908 #define bOFDMContinueTx 0x10000000 909 #define bOFDMSingleCarrier 0x20000000 910 #define bOFDMSingleTone 0x40000000 911 //#define bRxPath1 0x01 912 //#define bRxPath2 0x02 913 //#define bRxPath3 0x04 914 //#define bRxPath4 0x08 915 //#define bTxPath1 0x10 916 //#define bTxPath2 0x20 917 #define bHTDetect 0x100 918 #define bCFOEn 0x10000 919 #define bCFOValue 0xfff00000 920 #define bSigTone_Re 0x3f 921 #define bSigTone_Im 0x7f00 922 #define bCounter_CCA 0xffff 923 #define bCounter_ParityFail 0xffff0000 924 #define bCounter_RateIllegal 0xffff 925 #define bCounter_CRC8Fail 0xffff0000 926 #define bCounter_MCSNoSupport 0xffff 927 #define bCounter_FastSync 0xffff 928 #define bShortCFO 0xfff 929 #define bShortCFOTLength 12 //total 930 #define bShortCFOFLength 11 //fraction 931 #define bLongCFO 0x7ff 932 #define bLongCFOTLength 11 933 #define bLongCFOFLength 11 934 #define bTailCFO 0x1fff 935 #define bTailCFOTLength 13 936 #define bTailCFOFLength 12 937 #define bmax_en_pwdB 0xffff 938 #define bCC_power_dB 0xffff0000 939 #define bnoise_pwdB 0xffff 940 #define bPowerMeasTLength 10 941 #define bPowerMeasFLength 3 942 #define bRx_HT_BW 0x1 943 #define bRxSC 0x6 944 #define bRx_HT 0x8 945 #define bNB_intf_det_on 0x1 946 #define bIntf_win_len_cfg 0x30 947 #define bNB_Intf_TH_cfg 0x1c0 948 #define bRFGain 0x3f 949 #define bTableSel 0x40 950 #define bTRSW 0x80 951 #define bRxSNR_A 0xff 952 #define bRxSNR_B 0xff00 953 #define bRxSNR_C 0xff0000 954 #define bRxSNR_D 0xff000000 955 #define bSNREVMTLength 8 956 #define bSNREVMFLength 1 957 #define bCSI1st 0xff 958 #define bCSI2nd 0xff00 959 #define bRxEVM1st 0xff0000 960 #define bRxEVM2nd 0xff000000 961 #define bSIGEVM 0xff 962 #define bPWDB 0xff00 963 #define bSGIEN 0x10000 964 965 #define bSFactorQAM1 0xf // Useless 966 #define bSFactorQAM2 0xf0 967 #define bSFactorQAM3 0xf00 968 #define bSFactorQAM4 0xf000 969 #define bSFactorQAM5 0xf0000 970 #define bSFactorQAM6 0xf0000 971 #define bSFactorQAM7 0xf00000 972 #define bSFactorQAM8 0xf000000 973 #define bSFactorQAM9 0xf0000000 974 #define bCSIScheme 0x100000 975 976 #define bNoiseLvlTopSet 0x3 // Useless 977 #define bChSmooth 0x4 978 #define bChSmoothCfg1 0x38 979 #define bChSmoothCfg2 0x1c0 980 #define bChSmoothCfg3 0xe00 981 #define bChSmoothCfg4 0x7000 982 #define bMRCMode 0x800000 983 #define bTHEVMCfg 0x7000000 984 985 #define bLoopFitType 0x1 // Useless 986 #define bUpdCFO 0x40 987 #define bUpdCFOOffData 0x80 988 #define bAdvUpdCFO 0x100 989 #define bAdvTimeCtrl 0x800 990 #define bUpdClko 0x1000 991 #define bFC 0x6000 992 #define bTrackingMode 0x8000 993 #define bPhCmpEnable 0x10000 994 #define bUpdClkoLTF 0x20000 995 #define bComChCFO 0x40000 996 #define bCSIEstiMode 0x80000 997 #define bAdvUpdEqz 0x100000 998 #define bUChCfg 0x7000000 999 #define bUpdEqz 0x8000000 1000 1001 //Rx Pseduo noise 1002 #define bRxPesudoNoiseOn 0x20000000 // Useless 1003 #define bRxPesudoNoise_A 0xff 1004 #define bRxPesudoNoise_B 0xff00 1005 #define bRxPesudoNoise_C 0xff0000 1006 #define bRxPesudoNoise_D 0xff000000 1007 #define bPesudoNoiseState_A 0xffff 1008 #define bPesudoNoiseState_B 0xffff0000 1009 #define bPesudoNoiseState_C 0xffff 1010 #define bPesudoNoiseState_D 0xffff0000 1011 1012 //7. RF Register 1013 //Zebra1 1014 #define bZebra1_HSSIEnable 0x8 // Useless 1015 #define bZebra1_TRxControl 0xc00 1016 #define bZebra1_TRxGainSetting 0x07f 1017 #define bZebra1_RxCorner 0xc00 1018 #define bZebra1_TxChargePump 0x38 1019 #define bZebra1_RxChargePump 0x7 1020 #define bZebra1_ChannelNum 0xf80 1021 #define bZebra1_TxLPFBW 0x400 1022 #define bZebra1_RxLPFBW 0x600 1023 1024 //Zebra4 1025 #define bRTL8256RegModeCtrl1 0x100 // Useless 1026 #define bRTL8256RegModeCtrl0 0x40 1027 #define bRTL8256_TxLPFBW 0x18 1028 #define bRTL8256_RxLPFBW 0x600 1029 1030 //RTL8258 1031 #define bRTL8258_TxLPFBW 0xc // Useless 1032 #define bRTL8258_RxLPFBW 0xc00 1033 #define bRTL8258_RSSILPFBW 0xc0 1034 1035 1036 // 1037 // Other Definition 1038 // 1039 1040 //byte endable for sb_write 1041 #define bByte0 0x1 // Useless 1042 #define bByte1 0x2 1043 #define bByte2 0x4 1044 #define bByte3 0x8 1045 #define bWord0 0x3 1046 #define bWord1 0xc 1047 #define bDWord 0xf 1048 1049 //for PutRegsetting & GetRegSetting BitMask 1050 #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f 1051 #define bMaskByte1 0xff00 1052 #define bMaskByte2 0xff0000 1053 #define bMaskByte3 0xff000000 1054 #define bMaskHWord 0xffff0000 1055 #define bMaskLWord 0x0000ffff 1056 #define bMaskDWord 0xffffffff 1057 #define bMaskH3Bytes 0xffffff00 1058 #define bMask12Bits 0xfff 1059 #define bMaskH4Bits 0xf0000000 1060 #define bMaskOFDM_D 0xffc00000 1061 #define bMaskCCK 0x3f3f3f3f 1062 1063 1064 1065 #define bEnable 0x1 // Useless 1066 #define bDisable 0x0 1067 1068 #define LeftAntenna 0x0 // Useless 1069 #define RightAntenna 0x1 1070 1071 #define tCheckTxStatus 500 //500ms // Useless 1072 #define tUpdateRxCounter 100 //100ms 1073 1074 #define rateCCK 0 // Useless 1075 #define rateOFDM 1 1076 #define rateHT 2 1077 1078 //define Register-End 1079 #define bPMAC_End 0x1ff // Useless 1080 #define bFPGAPHY0_End 0x8ff 1081 #define bFPGAPHY1_End 0x9ff 1082 #define bCCKPHY0_End 0xaff 1083 #define bOFDMPHY0_End 0xcff 1084 #define bOFDMPHY1_End 0xdff 1085 1086 //define max debug item in each debug page 1087 //#define bMaxItem_FPGA_PHY0 0x9 1088 //#define bMaxItem_FPGA_PHY1 0x3 1089 //#define bMaxItem_PHY_11B 0x16 1090 //#define bMaxItem_OFDM_PHY0 0x29 1091 //#define bMaxItem_OFDM_PHY1 0x0 1092 1093 #define bPMACControl 0x0 // Useless 1094 #define bWMACControl 0x1 1095 #define bWNICControl 0x2 1096 1097 #define PathA 0x0 // Useless 1098 #define PathB 0x1 1099 #define PathC 0x2 1100 #define PathD 0x3 1101 1102 /*--------------------------Define Parameters-------------------------------*/ 1103 1104 1105 #endif 1106 1107