1*4882a593SmuzhiyunOMAP SSI controller bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunOMAP3's Synchronous Serial Interface (SSI) controller implements a 4*4882a593Smuzhiyunlegacy variant of MIPI's High Speed Synchronous Serial Interface (HSI), 5*4882a593Smuzhiyunwhile the controller found inside OMAP4 is supposed to be fully compliant 6*4882a593Smuzhiyunwith the HSI standard. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi" 10*4882a593Smuzhiyun- reg-names: Contains the values "sys" and "gdd" (in this order). 11*4882a593Smuzhiyun- reg: Contains a matching register specifier for each entry 12*4882a593Smuzhiyun in reg-names. 13*4882a593Smuzhiyun- interrupt-names: Contains the value "gdd_mpu". 14*4882a593Smuzhiyun- interrupts: Contains matching interrupt information for each entry 15*4882a593Smuzhiyun in interrupt-names. 16*4882a593Smuzhiyun- ranges: Represents the bus address mapping between the main 17*4882a593Smuzhiyun controller node and the child nodes below. 18*4882a593Smuzhiyun- clock-names: Must include the following entries: 19*4882a593Smuzhiyun "ssi_ssr_fck": The OMAP clock of that name 20*4882a593Smuzhiyun "ssi_sst_fck": The OMAP clock of that name 21*4882a593Smuzhiyun "ssi_ick": The OMAP clock of that name 22*4882a593Smuzhiyun- clocks: Contains a matching clock specifier for each entry in 23*4882a593Smuzhiyun clock-names. 24*4882a593Smuzhiyun- #address-cells: Should be set to <1> 25*4882a593Smuzhiyun- #size-cells: Should be set to <1> 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunEach port is represented as a sub-node of the ti,omap3-ssi device. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunRequired Port sub-node properties: 30*4882a593Smuzhiyun- compatible: Should be set to the following value 31*4882a593Smuzhiyun ti,omap3-ssi-port (applicable to OMAP34xx devices) 32*4882a593Smuzhiyun ti,omap4-hsi-port (applicable to OMAP44xx devices) 33*4882a593Smuzhiyun- reg-names: Contains the values "tx" and "rx" (in this order). 34*4882a593Smuzhiyun- reg: Contains a matching register specifier for each entry 35*4882a593Smuzhiyun in reg-names. 36*4882a593Smuzhiyun- interrupts: Should contain interrupt specifiers for mpu interrupts 37*4882a593Smuzhiyun 0 and 1 (in this order). 38*4882a593Smuzhiyun- ti,ssi-cawake-gpio: Defines which GPIO pin is used to signify CAWAKE 39*4882a593Smuzhiyun events for the port. This is an optional board-specific 40*4882a593Smuzhiyun property. If it's missing the port will not be 41*4882a593Smuzhiyun enabled. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunOptional properties: 44*4882a593Smuzhiyun- ti,hwmods: Shall contain TI interconnect module name if needed 45*4882a593Smuzhiyun by the SoC 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunExample for Nokia N900: 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunssi-controller@48058000 { 50*4882a593Smuzhiyun compatible = "ti,omap3-ssi"; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* needed until hwmod is updated to use the compatible string */ 53*4882a593Smuzhiyun ti,hwmods = "ssi"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun reg = <0x48058000 0x1000>, 56*4882a593Smuzhiyun <0x48059000 0x1000>; 57*4882a593Smuzhiyun reg-names = "sys", 58*4882a593Smuzhiyun "gdd"; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun interrupts = <55>; 61*4882a593Smuzhiyun interrupt-names = "gdd_mpu"; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun clocks = <&ssi_ssr_fck>, 64*4882a593Smuzhiyun <&ssi_sst_fck>, 65*4882a593Smuzhiyun <&ssi_ick>; 66*4882a593Smuzhiyun clock-names = "ssi_ssr_fck", 67*4882a593Smuzhiyun "ssi_sst_fck", 68*4882a593Smuzhiyun "ssi_ick"; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #address-cells = <1>; 71*4882a593Smuzhiyun #size-cells = <1>; 72*4882a593Smuzhiyun ranges; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun ssi-port@4805a000 { 75*4882a593Smuzhiyun compatible = "ti,omap3-ssi-port"; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun reg = <0x4805a000 0x800>, 78*4882a593Smuzhiyun <0x4805a800 0x800>; 79*4882a593Smuzhiyun reg-names = "tx", 80*4882a593Smuzhiyun "rx"; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun interrupt-parent = <&intc>; 83*4882a593Smuzhiyun interrupts = <67>, 84*4882a593Smuzhiyun <68>; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ 87*4882a593Smuzhiyun } 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun ssi-port@4805a000 { 90*4882a593Smuzhiyun compatible = "ti,omap3-ssi-port"; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun reg = <0x4805b000 0x800>, 93*4882a593Smuzhiyun <0x4805b800 0x800>; 94*4882a593Smuzhiyun reg-names = "tx", 95*4882a593Smuzhiyun "rx"; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun interrupt-parent = <&intc>; 98*4882a593Smuzhiyun interrupts = <69>, 99*4882a593Smuzhiyun <70>; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun } 102*4882a593Smuzhiyun} 103