1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */ 4 5 #ifndef __NAND_H 6 #define __NAND_H 7 8 #include <linux/io.h> 9 10 #define nandc_writel(v, offs) writel((v), (offs) + nandc_base) 11 #define nandc_readl(offs) readl((offs) + nandc_base) 12 13 #define NANDC_READ 0 14 #define NANDC_WRITE 1 15 #define RK3326_NANDC_VER 0x56393030 16 17 /* INT ID */ 18 enum NANDC_IRQ_NUM_T { 19 NC_IRQ_DMA = 0, 20 NC_IRQ_FRDY, 21 NC_IRQ_BCHERR, 22 NC_IRQ_BCHFAIL, 23 NC_IRQ_LLP 24 }; 25 26 enum ENUM_NANDC_BCH_CFG { 27 NC_BCH_70 = 0, 28 NC_BCH_24, 29 NC_BCH_40, 30 NC_BCH_60, 31 }; 32 33 union FM_CTL_T { 34 u32 d32; 35 struct { 36 unsigned cs : 8; /* bits[0:7] */ 37 unsigned wp : 1; /* bits[8] */ 38 unsigned rdy : 1; /* bits[9] */ 39 unsigned fifo_empty : 1; /* bits[10] */ 40 unsigned reserved11 : 1; /* bits[11] */ 41 unsigned dwidth : 1; /* bits[12] */ 42 unsigned tm : 1; /* bits[13] */ 43 unsigned onficlk_en : 1; /* bits[14] */ 44 unsigned toggle_en : 1; /* bits[15] */ 45 unsigned flash_abort_en : 1; /* bits[16] */ 46 unsigned flash_abort_clear : 1; /* bits[17] */ 47 unsigned reserved18_23 : 6; /* bits[18:23] */ 48 unsigned read_delay : 3; /* bits[24:26] */ 49 unsigned reserved27_31 : 5; /* bits[27:31] */ 50 } V6; 51 struct { 52 unsigned cs : 8; 53 unsigned wp : 1; 54 unsigned frdy : 1; 55 unsigned fifo_empth_flash : 1; 56 unsigned reserved11_12 : 2; 57 unsigned tm : 1; 58 unsigned syn_clken : 1; 59 unsigned syn_mode : 1; 60 unsigned flash_abort_en : 1; 61 unsigned flash_abort_clear : 1; 62 unsigned sif_read_delay : 3; 63 unsigned io_mux : 3; 64 unsigned reserved24_31 : 8; 65 } V9; 66 }; 67 68 union FM_WAIT_T { 69 u32 d32; 70 struct { 71 unsigned csrw : 5; 72 unsigned rwpw : 6; 73 unsigned rdy : 1; 74 unsigned rwcs : 6; 75 unsigned reserved18_23 : 6; 76 unsigned fmw_dly : 6; 77 unsigned fmw_dly_en : 1; 78 unsigned reserved31_31 : 1; 79 } V6; 80 struct { 81 unsigned rwcs : 5; 82 unsigned rwpw : 6; 83 unsigned hard_rdy : 1; 84 unsigned csrw : 6; 85 unsigned wait_frdy_dly : 5; 86 unsigned reserved23_23 : 1; 87 unsigned fmw_dly : 6; 88 unsigned fmw_dly_en : 1; 89 unsigned reserved31_31 : 1; 90 } V9; 91 }; 92 93 union FL_CTL_T { 94 u32 d32; 95 struct { 96 unsigned rst : 1; 97 unsigned rdn : 1; 98 unsigned start : 1; 99 unsigned dma : 1; 100 unsigned st_addr : 1; 101 unsigned tr_count : 2; 102 unsigned rdy_ignore : 1; 103 /* unsigned int_clr : 1; */ 104 /* unsigned int_en : 1; */ 105 unsigned reserved8_9 : 2; 106 unsigned cor_en : 1; 107 unsigned lba_en : 1; 108 unsigned spare_size : 7; 109 unsigned reserved19 : 1; 110 unsigned tr_rdy : 1; 111 unsigned page_size : 1; 112 unsigned page_num : 6; 113 unsigned low_power : 1; 114 unsigned async_tog_mix : 1; 115 unsigned reserved30_31 : 2; 116 } V6; 117 struct { 118 unsigned flash_rst : 1; 119 unsigned flash_rdn : 1; 120 unsigned flash_st : 1; 121 unsigned bypass : 1; 122 unsigned st_addr : 1; 123 unsigned tr_count : 2; 124 unsigned flash_st_mod : 1; 125 unsigned not_tran_data : 1; 126 unsigned tran_seed : 1; 127 unsigned cor_able : 1; 128 unsigned lba_en : 1; 129 unsigned lba_spare_sel : 1; 130 unsigned reserved13_18 : 6; 131 unsigned bchst_trans : 1; 132 unsigned tr_rdy : 1; 133 unsigned page_size : 1; 134 unsigned page_num : 6; 135 unsigned low_power : 1; 136 unsigned async_tog_mix : 1; 137 unsigned bypass_fifo_mode : 1; 138 unsigned reserved31_31 : 1; 139 } V9; 140 }; 141 142 union BCH_CTL_T { 143 u32 d32; 144 struct { 145 unsigned rst : 1; 146 unsigned reserved : 1; 147 unsigned addr_not_care : 1; 148 unsigned power_down : 1; 149 unsigned bch_mode : 1; /* 0-16bit/1KB, 1-24bit/1KB */ 150 unsigned region : 3; 151 unsigned addr : 8; 152 unsigned bchpage : 1; 153 unsigned reserved17 : 1; 154 unsigned bch_mode1 : 1; 155 unsigned thres : 8; 156 unsigned reserved27_31 : 5; 157 } V6; 158 struct { 159 unsigned bchrst : 1; 160 unsigned wcnt_clear : 1; 161 unsigned reserved2 : 1; 162 unsigned bchepd : 1; 163 unsigned reserved4_15 : 12; 164 unsigned bchpage : 1; 165 unsigned bchthre : 8; 166 unsigned bchmode : 3; 167 unsigned reserved28_31 : 4; 168 } V9; 169 }; 170 171 union BCH_ST_T { 172 u32 d32; 173 struct { 174 unsigned errf0 : 1; 175 unsigned done0 : 1; 176 unsigned fail0 : 1; 177 unsigned err_bits0 : 5; 178 unsigned err_bits_low0 : 5; 179 unsigned errf1 : 1; 180 unsigned done1 : 1; 181 unsigned fail1 : 1; 182 unsigned err_bits1 : 5; 183 unsigned err_bits_low1 : 5; 184 unsigned rdy : 1; 185 /* unsigned cnt : 1; */ 186 unsigned err_bits0_5 : 1; 187 unsigned err_bits_low0_5 : 1; 188 unsigned err_bits1_5 : 1; 189 unsigned err_bits_low1_5 : 1; 190 unsigned reserved31_31 : 1; 191 } V6; 192 struct { 193 unsigned errf0 : 1; 194 unsigned done0 : 1; 195 unsigned fail0 : 1; 196 unsigned err_bits0 : 7; 197 unsigned all_f_flag0 : 1; 198 unsigned reserved11_15 : 5; 199 unsigned errf1 : 1; 200 unsigned done1 : 1; 201 unsigned fail1 : 1; 202 unsigned err_bits1 : 7; 203 unsigned all_f_flag1 : 1; 204 unsigned reserved27_30 : 4; 205 unsigned bch_ready_flag: 1; 206 } V9; 207 }; 208 209 union MTRANS_CFG_T { 210 u32 d32; 211 struct { 212 unsigned ahb_wr_st : 1; 213 unsigned ahb_wr : 1; 214 unsigned bus_mode : 1; 215 unsigned hsize : 3; 216 unsigned burst : 3; 217 unsigned incr_num : 5; 218 unsigned fl_pwd : 1; 219 unsigned ahb_rst : 1; 220 unsigned reserved16_31 : 16; 221 } V6; 222 struct { 223 unsigned ahb_wr_st : 1; 224 unsigned ahb_wr : 1; 225 unsigned bus_mode : 1; 226 unsigned hsize : 3; 227 unsigned burst : 3; 228 unsigned incr_num : 5; 229 unsigned fl_pwd : 1; 230 unsigned ahb_rst : 1; 231 unsigned redundance_size : 11; 232 unsigned reserved27_31 : 5; 233 } V9; 234 }; 235 236 union MTRANS_STAT_T { 237 u32 d32; 238 struct { 239 unsigned bus_err : 16; 240 unsigned mtrans_cnt : 5; 241 unsigned reserved21_31 : 11; 242 } V6; 243 struct { 244 unsigned bus_err : 16; 245 unsigned mtrans_cnt : 6; 246 unsigned reserved22_31 : 10; 247 } V9; 248 }; 249 250 /* NANDC Registers */ 251 #define NANDC_FMCTL 0x0 252 #define NANDC_FMWAIT 0x4 253 #define NANDC_FLCTL 0x8 254 #define NANDC_BCHCTL 0xc 255 #define NANDC_MTRANS_CFG 0x10 256 #define NANDC_MTRANS_SADDR0 0x14 257 #define NANDC_MTRANS_SADDR1 0x18 258 #define NANDC_MTRANS_STAT 0x1c 259 #define NANDC_DLL_CTL_REG0 0x130 260 #define NANDC_DLL_CTL_REG1 0x134 261 #define NANDC_DLL_OBS_REG0 0x138 262 #define NANDC_RANDMZ_CFG 0x150 263 #define NANDC_EBI_EN 0x154 264 #define NANDC_FMWAIT_SYN 0x158 265 #define NANDC_MTRANS_STAT2 0x15c 266 #define NANDC_NANDC_VER 0x160 267 #define NANDC_LLP_CTL 0x164 268 #define NANDC_LLP_STAT 0x168 269 #define NANDC_INTEN 0x16c 270 #define NANDC_INTCLR 0x170 271 #define NANDC_INTST 0x174 272 #define NANDC_SPARE0 0x200 273 #define NANDC_SPARE1 0x230 274 275 #define NANDC_BCHST(i) ({ \ 276 u32 x = (i); \ 277 4 * x + x < 8 ? 0x20 : 0x520; }) 278 279 #define NANDC_CHIP_DATA(id) (0x800 + (id) * 0x100) 280 #define NANDC_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4) 281 #define NANDC_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8) 282 283 #define NANDC_V9_FMCTL 0x0 284 #define NANDC_V9_FMWAIT 0x4 285 #define NANDC_V9_FLCTL 0x10 286 #define NANDC_V9_BCHCTL 0x20 287 #define NANDC_V9_MTRANS_CFG 0x30 288 #define NANDC_V9_MTRANS_SADDR0 0x34 289 #define NANDC_V9_MTRANS_SADDR1 0x38 290 #define NANDC_V9_MTRANS_STAT 0x40 291 #define NANDC_V9_MTRANS_STAT2 0x44 292 #define NANDC_V9_NANDC_VER 0x80 293 294 #define NANDC_V9_INTEN 0x120 295 #define NANDC_V9_INTCLR 0x124 296 #define NANDC_V9_INTST 0x128 297 #define NANDC_V9_SPARE0 0x200 298 #define NANDC_V9_SPARE1 0x204 299 #define NANDC_V9_RANDMZ_CFG 0x208 300 #define NANDC_V9_BCHST(i) (0x150 + (i) * 4) 301 302 #define NANDC_V9_CHIP_DATA(id) (0x800 + (id) * 0x100) 303 #define NANDC_V9_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4) 304 #define NANDC_V9_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8) 305 306 struct MASTER_INFO_T { 307 u32 *page_buf; /* [DATA_LEN]; */ 308 u32 *spare_buf; /* [DATA_LEN / (1024/128)]; */ 309 u32 *page_vir; /* page_buf_vir_addr */ 310 u32 *spare_vir; /* spare_buf_vir_addr */ 311 u32 page_phy; /* page_buf_phy_addr */ 312 u32 spare_phy; /* spare_buf_phy_addr*/ 313 u32 mapped; 314 u32 cnt; 315 }; 316 317 struct CHIP_MAP_INFO_T { 318 u32 *nandc_addr; 319 u32 chip_num; 320 }; 321 322 unsigned long rknandc_dma_map_single(unsigned long ptr, 323 int size, 324 int dir); 325 void rknandc_dma_unmap_single(unsigned long ptr, 326 int size, 327 int dir); 328 329 void nandc_init(void __iomem *nandc_addr); 330 void nandc_flash_cs(u8 chip_sel); 331 void nandc_flash_de_cs(u8 chip_sel); 332 u32 nandc_wait_flash_ready(u8 chip_sel); 333 u32 nandc_delayns(u32 count); 334 u32 nandc_xfer_data(u8 chip_sel, 335 u8 dir, 336 u8 sector_count, 337 u32 *p_data, 338 u32 *p_spare); 339 void nandc_randmz_sel(u8 chip_sel, u32 randmz_seed); 340 void nandc_bch_sel(u8 bits); 341 void nandc_read_not_case_busy_en(u8 en); 342 void nandc_time_cfg(u32 ns); 343 void nandc_clean_irq(void); 344 u8 nandc_get_version(void); 345 346 #endif 347