Lines Matching +full:0 +full:x800
9 #define RV1106_WAKEUP_TO_SYSTEM_RESET 0
11 #define RV1106_PERIGRF_OFFSET 0x0
12 #define RV1106_VENCGRF_OFFSET 0x10000
13 #define RV1106_NPUGRF_OFFSET 0x18000
14 #define RV1106_PMUGRF_OFFSET 0x20000
15 #define RV1106_DDRGRF_OFFSET 0x30000
16 #define RV1106_COREGRF_OFFSET 0x40000
17 #define RV1106_VIGRF_OFFSET 0x50000
18 #define RV1106_VOGRF_OFFSET 0x60000
20 #define RV1106_PERISGRF_OFFSET 0x70000
21 #define RV1106_VISGRF_OFFSET 0x72000
22 #define RV1106_NPUSGRF_OFFSET 0x74000
23 #define RV1106_CORESGRF_OFFSET 0x76000
24 #define RV1106_VENCSGRF_OFFSET 0x78000
25 #define RV1106_VOSGRF_OFFSET 0x7a000
26 #define RV1106_PMUSGRF_OFFSET 0x80000
28 #define RV1106_GIC_OFFSET 0x1f0000
29 #define RV1106_HPTIMER_OFFSET 0x2f0000
30 #define RV1106_PMU_OFFSET 0x300000
31 #define RV1106_GPIO0_OFFSET 0x380000
32 #define RV1106_GPIO0IOC_OFFSET 0x388000
33 #define RV1106_PMUPVTM_OFFSET 0x390000
35 #define RV1106_PMUCRU_OFFSET 0x3a0000
36 #define RV1106_CRU_OFFSET 0x3b0000
37 #define RV1106_PERICRU_OFFSET 0x3b2000
38 #define RV1106_VICRU_OFFSET 0x3b4000
39 #define RV1106_NPUCRU_OFFSET 0x3b6000
40 #define RV1106_CORECRU_OFFSET 0x3b8000
41 #define RV1106_VENCCRU_OFFSET 0x3ba000
42 #define RV1106_VOCRU_OFFSET 0x3bc000
44 #define RV1106_UART2_OFFSET 0x4c0000
46 #define RV1106_GPIO1_OFFSET 0x530000
47 #define RV1106_GPIO1IOC_OFFSET 0x538000
48 #define RV1106_GPIO2_OFFSET 0x540000
49 #define RV1106_GPIO2IOC_OFFSET 0x548000
50 #define RV1106_GPIO3_OFFSET 0x550000
51 #define RV1106_GPIO3IOC_OFFSET 0x558000
52 #define RV1106_GPIO4_OFFSET 0x560000
53 #define RV1106_GPIO4IOC_OFFSET 0x568000
55 #define RV1106_NSTIMER_OFFSET 0x580000
56 #define RV1106_STIMER_OFFSET 0x590000
57 #define RV1106_PMUSRAM_OFFSET 0x670000
58 #define RV1106_DDRC_OFFSET 0x800000
59 #define RV1106_FW_DDR_OFFSET 0x900000
60 #define RV1106_FW_SRAM_OFFSET 0x910000
62 #define RV1106_DEV_REG_BASE 0xff000000
63 #define RV1106_DEV_REG_SIZE 0x920000
69 #define RV1106_CRU_PLL_CON(pll_id, i) ((pll_id) * 0x20 + (i) * 4)
70 #define RV1106_CRU_MODE_CON00 0x280
71 #define RV1106_CRU_GATE_CON(i) (0x800 + (i) * 4)
77 #define RV1106_PMUCRU_GATE_CON(i) (0x800 + (i) * 4)
78 #define RV1106_PMUCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
81 #define RV1106_PERICRU_GATE_CON(i) (0x800 + (i) * 4)
82 #define RV1106_PERICRU_CLKSEL_CON(i) (0x300 + (i) * 4)
85 #define RV1106_NPUCRU_GATE_CON(i) (0x800 + (i) * 4)
86 #define RV1106_NPUCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
89 #define RV1106_VENCCRU_GATE_CON(i) (0x800 + (i) * 4)
90 #define RV1106_VENCCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
93 #define RV1106_VICRU_GATE_CON(i) (0x800 + (i) * 4)
94 #define RV1106_VICRU_CLKSEL_CON(i) (0x300 + (i) * 4)
97 #define RV1106_VOCRU_GATE_CON(i) (0x800 + (i) * 4)
98 #define RV1106_VOCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
101 #define RV1106_CORECRU_GATE_CON(i) (0x800 + (i) * 4)
102 #define RV1106_COERCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
107 #define RV1106_PMUGRF_OS_REG(i) (0x200 + (i) * 4)
111 #define RV1106_DDRGRF_CON(i) ((i) * 0x4)
114 #define RV1106_PVTM_CON(i) (0x4 + (i) * 4)
115 #define RV1106_PVTM_INTEN 0x70
116 #define RV1106_PVTM_INTSTS 0x74
117 #define RV1106_PVTM_STATUS(i) (0x80 + (i) * 4)
119 #define RV1106_PVTM_CALC_CNT 0x200
122 #define RV1106_GPIO_SWPORT_DR_L 0x0000
123 #define RV1106_GPIO_SWPORT_DR_H 0x0004
124 #define RV1106_GPIO_SWPORT_DDR_L 0x0008
125 #define RV1106_GPIO_SWPORT_DDR_H 0x000c
126 #define RV1106_GPIO_INT_EN_L 0x0010
127 #define RV1106_GPIO_INT_EN_H 0x0014
128 #define RV1106_GPIO_INT_MASK_L 0x0018
129 #define RV1106_GPIO_INT_MASK_H 0x001c
130 #define RV1106_GPIO_INT_TYPE_L 0x0020
131 #define RV1106_GPIO_INT_TYPE_H 0x0024
132 #define RV1106_GPIO_INT_POLARITY_L 0x0028
133 #define RV1106_GPIO_INT_POLARITY_H 0x002c
134 #define RV1106_GPIO_INT_BOTHEDGE_L 0x0030
135 #define RV1106_GPIO_INT_BOTHEDGE_H 0x0034
136 #define RV1106_GPIO_DEBOUNCE_L 0x0038
137 #define RV1106_GPIO_DEBOUNCE_H 0x003c
138 #define RV1106_GPIO_DBCLK_DIV_EN_L 0x0040
139 #define RV1106_GPIO_DBCLK_DIV_EN_H 0x0044
140 #define RV1106_GPIO_DBCLK_DIV_CON 0x0048
141 #define RV1106_GPIO_INT_STATUS 0x0050
142 #define RV1106_GPIO_INT_RAWSTATUS 0x0058
145 #define RV1106_PMU_VERSION 0x000
146 #define RV1106_PMU_PWR_CON 0x004
147 #define RV1106_PMU_GLB_POWER_STS 0x008
148 #define RV1106_PMU_INT_MASK_CON 0x00c
149 #define RV1106_PMU_WAKEUP_INT_CON 0x010
150 #define RV1106_PMU_WAKEUP_INT_ST 0x014
151 #define RV1106_PMU_PMIC_STABLE_CNT 0x024
152 #define RV1106_PMU_OSC_STABLE_CNT 0x028
153 #define RV1106_PMU_WAKEUP_RSTCLR_CNT 0x02c
154 #define RV1106_PMU_PLL_LOCK_CNT 0x030
155 #define RV1106_PMU_WAKEUP_TIMEOUT_CNT 0x048
156 #define RV1106_PMU_PWM_SWITCH_CNT 0x04c
157 #define RV1106_PMU_SCU_PWR_CON 0x080
158 #define RV1106_PMU_SCU_STS 0x084
159 #define RV1106_PMU_BIU_IDLE_CON 0x0b0
160 #define RV1106_PMU_BIU_IDLE_SFTCON 0x0c0
161 #define RV1106_PMU_BIU_IDLE_ACK 0x0d0
162 #define RV1106_PMU_BIU_IDLE_ST 0x0d8
163 #define RV1106_PMU_BIU_AUTO_CON 0x0e0
164 #define RV1106_PMU_DDR_PWR_CON 0x0f0
165 #define RV1106_PMU_DDR_PWR_SFTCON 0x0f4
166 #define RV1106_PMU_DDR_POWER_STS 0x0f8
167 #define RV1106_PMU_DDR_STS 0x0fC
168 #define RV1106_PMU_CRU_PWR_CON0 0x120
169 #define RV1106_PMU_CRU_PWR_CON1 0x140
170 #define RV1106_PMU_CRU_PWR_SFTCON 0x124
171 #define RV1106_PMU_CRU_POWER_STS 0x128
172 #define RV1106_PMU_PLLPD_CON 0x130
173 #define RV1106_PMU_PLLPD_SFTCON 0x134
174 #define RV1106_PMU_INFO_TX_CON 0x150
175 #define RV1106_PMU_SYS_REG(i) (0x1c0 + (i) * 4)
177 #define PMU_SUSPEND_MAGIC 0x02468ace
178 #define PMU_RESUME_MAGIC 0x13579bdf
201 RV1106_PMU_PWRMODE_EN = 0,
208 RV1106_PMU_GLB_INT_MASK = 0,
212 RV1106_PMU_WAKEUP_CPU_INT_EN = 0,
224 RV1106_PMU_SCU_INT_MASK_ENA = 0,
235 RV1106_PMU_IDLE_REQ_MSCH = 0,
251 RV1106_PMU_AUTO_IDLE_MSCH = 0,
267 RV1106_PMU_DDR_SREF_C_ENA = 0,
278 RV1106_PMU_ALIVE_32K_ENA = 0,
291 RV1106_PMU_VI_CLK_SRC_GATE_ENA = 0,
303 RV1106_PMU_APLL_PD_ENA = 0,
310 RV1106_APLL_ID = 0,
317 PVTM_START = 0,