Searched +full:0 +full:x53f80000 (Results 1 – 13 of 13) sorted by relevance
19 ckih 0128 reg = <0x53f80000 0x4000>;135 reg = <0x53fb4000 0x4000>;
19 dummy 0109 reg = <0x53f80000 0x4000>;116 reg = <0x43f90000 0x4000>;
19 dummy 0175 reg = <0x53f80000 0x4000>;182 reg = <0x43f90000 0x4000>;
19 #define MX31_CCM_BASE_ADDR 0x53f8000020 #define MX31_GPT1_BASE_ADDR 0x53f9000023 #define MXC_CCM_CCMR 0x0024 #define MXC_CCM_PDR0 0x0425 #define MXC_CCM_PDR1 0x0826 #define MXC_CCM_MPCTL 0x1027 #define MXC_CCM_UPCTL 0x1428 #define MXC_CCM_SRPCTL 0x1829 #define MXC_CCM_CGR0 0x2030 #define MXC_CCM_CGR1 0x24[all …]
18 #define MX35_CCM_BASE_ADDR 0x53f8000019 #define MX35_GPT1_BASE_ADDR 0x53f9000022 #define MXC_CCM_PDR0 0x0423 #define MX35_CCM_PDR2 0x0c24 #define MX35_CCM_PDR3 0x1025 #define MX35_CCM_PDR4 0x1426 #define MX35_CCM_MPCTL 0x1c27 #define MX35_CCM_PPCTL 0x2028 #define MX35_CCM_CGR0 0x2c29 #define MX35_CCM_CGR1 0x30[all …]
17 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */18 #define IRAM_SIZE 0x00020000 /* 128 KB */20 #define LOW_LEVEL_SRAM_STACK 0x1001E00025 #define AIPS1_BASE_ADDR 0x43F0000027 #define MAX_BASE_ADDR 0x43F0400028 #define EVTMON_BASE_ADDR 0x43F0800029 #define CLKCTL_BASE_ADDR 0x43F0C00030 #define I2C1_BASE_ADDR 0x43F8000031 #define I2C3_BASE_ADDR 0x43F8400032 #define ATA_BASE_ADDR 0x43F8C000[all …]
35 #size-cells = <0>;37 cpu@0 {40 reg = <0>;48 reg = <0x68000000 0x100000>;60 reg = <0x1fffc000 0x4000>;63 ranges = <0 0x1fffc000 0x4000>;70 reg = <0x43f00000 0x100000>;75 reg = <0x43f80000 0x4000>;79 #size-cells = <0>;85 reg = <0x43f84000 0x4000>;[all …]
39 #size-cells = <0>;41 cpu@0 {44 reg = <0>;52 reg = <0x68000000 0x10000000>;64 reg = <0x30000000 0x1000>;73 reg = <0x43f00000 0x100000>;78 #size-cells = <0>;80 reg = <0x43f80000 0x4000>;89 #size-cells = <0>;91 reg = <0x43f84000 0x4000>;[all …]
48 #size-cells = <0>;49 cpu@0 {52 reg = <0x0>;60 reg = <0x0fffc000 0x4000>;66 #clock-cells = <0>;72 #clock-cells = <0>;78 #clock-cells = <0>;79 clock-frequency = <0>;84 #clock-cells = <0>;89 usbphy0: usbphy-0 {[all …]
47 #size-cells = <0>;49 cpu@0 {52 reg = <0>;60 reg = <0x68000000 0x8000000>;66 #clock-cells = <0>;82 reg = <0x43f00000 0x100000>;87 reg = <0x43f00000 0x4000>;92 #size-cells = <0>;94 reg = <0x43f80000 0x4000>;103 #size-cells = <0>;[all …]
51 #size-cells = <0>;52 cpu0: cpu@0 {55 reg = <0x0>;84 reg = <0x0fffc000 0x4000>;90 #clock-cells = <0>;96 #clock-cells = <0>;102 #clock-cells = <0>;103 clock-frequency = <0>;108 #clock-cells = <0>;119 usbphy0: usbphy-0 {[all …]
28 u32 cgr0; /* Clock Gating Control 0 */34 u32 dcvr0; /* DPTC Comparator Value 0 */38 u32 ltr0; /* Load Tracking 0 */42 u32 ltbr0; /* Load Tracking Buffer 0 */44 u32 pcmr0; /* Power Management Control 0 */48 u32 lpimr0; /* Low Power Interrupt Mask 0 */54 u32 ctl0; /* control 0 */55 u32 cfg0; /* configuration 0 */105 u32 res1[0x1f1];107 u32 fuse_regs[0x20];[all …]
71 u32 res[0x1f1];73 u32 fuse_regs[0x20];74 u32 fuse_rsvd[0xe0];101 #define IOMUX_PADNUM_MASK 0x1ff108 PAD_CTL_NOLOOPBACK = 0x0 << 9,109 PAD_CTL_LOOPBACK = 0x1 << 9,110 PAD_CTL_PKE_NONE = 0x0 << 8,111 PAD_CTL_PKE_ENABLE = 0x1 << 8,112 PAD_CTL_PUE_KEEPER = 0x0 << 7,113 PAD_CTL_PUE_PUD = 0x1 << 7,[all …]