1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx31-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Clock bindings for Freescale i.MX31 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Fabio Estevam <fabio.estevam@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The clock consumer should specify the desired clock by having the clock 14*4882a593Smuzhiyun ID in its "clocks" phandle cell. The following is a full list of i.MX31 15*4882a593Smuzhiyun clocks and IDs. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun Clock ID 18*4882a593Smuzhiyun ----------------------- 19*4882a593Smuzhiyun dummy 0 20*4882a593Smuzhiyun ckih 1 21*4882a593Smuzhiyun ckil 2 22*4882a593Smuzhiyun mpll 3 23*4882a593Smuzhiyun spll 4 24*4882a593Smuzhiyun upll 5 25*4882a593Smuzhiyun mcu_main 6 26*4882a593Smuzhiyun hsp 7 27*4882a593Smuzhiyun ahb 8 28*4882a593Smuzhiyun nfc 9 29*4882a593Smuzhiyun ipg 10 30*4882a593Smuzhiyun per_div 11 31*4882a593Smuzhiyun per 12 32*4882a593Smuzhiyun csi_sel 13 33*4882a593Smuzhiyun fir_sel 14 34*4882a593Smuzhiyun csi_div 15 35*4882a593Smuzhiyun usb_div_pre 16 36*4882a593Smuzhiyun usb_div_post 17 37*4882a593Smuzhiyun fir_div_pre 18 38*4882a593Smuzhiyun fir_div_post 19 39*4882a593Smuzhiyun sdhc1_gate 20 40*4882a593Smuzhiyun sdhc2_gate 21 41*4882a593Smuzhiyun gpt_gate 22 42*4882a593Smuzhiyun epit1_gate 23 43*4882a593Smuzhiyun epit2_gate 24 44*4882a593Smuzhiyun iim_gate 25 45*4882a593Smuzhiyun ata_gate 26 46*4882a593Smuzhiyun sdma_gate 27 47*4882a593Smuzhiyun cspi3_gate 28 48*4882a593Smuzhiyun rng_gate 29 49*4882a593Smuzhiyun uart1_gate 30 50*4882a593Smuzhiyun uart2_gate 31 51*4882a593Smuzhiyun ssi1_gate 32 52*4882a593Smuzhiyun i2c1_gate 33 53*4882a593Smuzhiyun i2c2_gate 34 54*4882a593Smuzhiyun i2c3_gate 35 55*4882a593Smuzhiyun hantro_gate 36 56*4882a593Smuzhiyun mstick1_gate 37 57*4882a593Smuzhiyun mstick2_gate 38 58*4882a593Smuzhiyun csi_gate 39 59*4882a593Smuzhiyun rtc_gate 40 60*4882a593Smuzhiyun wdog_gate 41 61*4882a593Smuzhiyun pwm_gate 42 62*4882a593Smuzhiyun sim_gate 43 63*4882a593Smuzhiyun ect_gate 44 64*4882a593Smuzhiyun usb_gate 45 65*4882a593Smuzhiyun kpp_gate 46 66*4882a593Smuzhiyun ipu_gate 47 67*4882a593Smuzhiyun uart3_gate 48 68*4882a593Smuzhiyun uart4_gate 49 69*4882a593Smuzhiyun uart5_gate 50 70*4882a593Smuzhiyun owire_gate 51 71*4882a593Smuzhiyun ssi2_gate 52 72*4882a593Smuzhiyun cspi1_gate 53 73*4882a593Smuzhiyun cspi2_gate 54 74*4882a593Smuzhiyun gacc_gate 55 75*4882a593Smuzhiyun emi_gate 56 76*4882a593Smuzhiyun rtic_gate 57 77*4882a593Smuzhiyun firi_gate 58 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunproperties: 80*4882a593Smuzhiyun compatible: 81*4882a593Smuzhiyun const: fsl,imx31-ccm 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun reg: 84*4882a593Smuzhiyun maxItems: 1 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun interrupts: 87*4882a593Smuzhiyun description: CCM provides 2 interrupt requests, request 1 is to generate 88*4882a593Smuzhiyun interrupt for DVFS when a frequency change is requested, request 2 is 89*4882a593Smuzhiyun to generate interrupt for DPTC when a voltage change is requested. 90*4882a593Smuzhiyun items: 91*4882a593Smuzhiyun - description: CCM DVFS interrupt request 1 92*4882a593Smuzhiyun - description: CCM DPTC interrupt request 2 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun '#clock-cells': 95*4882a593Smuzhiyun const: 1 96*4882a593Smuzhiyun 97*4882a593Smuzhiyunrequired: 98*4882a593Smuzhiyun - compatible 99*4882a593Smuzhiyun - reg 100*4882a593Smuzhiyun - interrupts 101*4882a593Smuzhiyun - '#clock-cells' 102*4882a593Smuzhiyun 103*4882a593SmuzhiyunadditionalProperties: false 104*4882a593Smuzhiyun 105*4882a593Smuzhiyunexamples: 106*4882a593Smuzhiyun - | 107*4882a593Smuzhiyun clock-controller@53f80000 { 108*4882a593Smuzhiyun compatible = "fsl,imx31-ccm"; 109*4882a593Smuzhiyun reg = <0x53f80000 0x4000>; 110*4882a593Smuzhiyun interrupts = <31>, <53>; 111*4882a593Smuzhiyun #clock-cells = <1>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun serial@43f90000 { 115*4882a593Smuzhiyun compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 116*4882a593Smuzhiyun reg = <0x43f90000 0x4000>; 117*4882a593Smuzhiyun interrupts = <45>; 118*4882a593Smuzhiyun clocks = <&clks 10>, <&clks 30>; 119*4882a593Smuzhiyun clock-names = "ipg", "per"; 120*4882a593Smuzhiyun }; 121