xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/imx25.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun//
3*4882a593Smuzhiyun// Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
6*4882a593Smuzhiyun#include "imx25-pinfunc.h"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	#address-cells = <1>;
10*4882a593Smuzhiyun	#size-cells = <1>;
11*4882a593Smuzhiyun	/*
12*4882a593Smuzhiyun	 * The decompressor and also some bootloaders rely on a
13*4882a593Smuzhiyun	 * pre-existing /chosen node to be available to insert the
14*4882a593Smuzhiyun	 * command line and merge other ATAGS info.
15*4882a593Smuzhiyun	 */
16*4882a593Smuzhiyun	chosen {};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	aliases {
19*4882a593Smuzhiyun		ethernet0 = &fec;
20*4882a593Smuzhiyun		gpio0 = &gpio1;
21*4882a593Smuzhiyun		gpio1 = &gpio2;
22*4882a593Smuzhiyun		gpio2 = &gpio3;
23*4882a593Smuzhiyun		gpio3 = &gpio4;
24*4882a593Smuzhiyun		i2c0 = &i2c1;
25*4882a593Smuzhiyun		i2c1 = &i2c2;
26*4882a593Smuzhiyun		i2c2 = &i2c3;
27*4882a593Smuzhiyun		mmc0 = &esdhc1;
28*4882a593Smuzhiyun		mmc1 = &esdhc2;
29*4882a593Smuzhiyun		pwm0 = &pwm1;
30*4882a593Smuzhiyun		pwm1 = &pwm2;
31*4882a593Smuzhiyun		pwm2 = &pwm3;
32*4882a593Smuzhiyun		pwm3 = &pwm4;
33*4882a593Smuzhiyun		serial0 = &uart1;
34*4882a593Smuzhiyun		serial1 = &uart2;
35*4882a593Smuzhiyun		serial2 = &uart3;
36*4882a593Smuzhiyun		serial3 = &uart4;
37*4882a593Smuzhiyun		serial4 = &uart5;
38*4882a593Smuzhiyun		spi0 = &spi1;
39*4882a593Smuzhiyun		spi1 = &spi2;
40*4882a593Smuzhiyun		spi2 = &spi3;
41*4882a593Smuzhiyun		usb0 = &usbotg;
42*4882a593Smuzhiyun		usb1 = &usbhost1;
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	cpus {
46*4882a593Smuzhiyun		#address-cells = <1>;
47*4882a593Smuzhiyun		#size-cells = <0>;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		cpu@0 {
50*4882a593Smuzhiyun			compatible = "arm,arm926ej-s";
51*4882a593Smuzhiyun			device_type = "cpu";
52*4882a593Smuzhiyun			reg = <0>;
53*4882a593Smuzhiyun		};
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	asic: asic-interrupt-controller@68000000 {
57*4882a593Smuzhiyun		compatible = "fsl,imx25-asic", "fsl,avic";
58*4882a593Smuzhiyun		interrupt-controller;
59*4882a593Smuzhiyun		#interrupt-cells = <1>;
60*4882a593Smuzhiyun		reg = <0x68000000 0x8000000>;
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	clocks {
64*4882a593Smuzhiyun		osc {
65*4882a593Smuzhiyun			compatible = "fsl,imx-osc", "fixed-clock";
66*4882a593Smuzhiyun			#clock-cells = <0>;
67*4882a593Smuzhiyun			clock-frequency = <24000000>;
68*4882a593Smuzhiyun		};
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	soc {
72*4882a593Smuzhiyun		#address-cells = <1>;
73*4882a593Smuzhiyun		#size-cells = <1>;
74*4882a593Smuzhiyun		compatible = "simple-bus";
75*4882a593Smuzhiyun		interrupt-parent = <&asic>;
76*4882a593Smuzhiyun		ranges;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun		bus@43f00000 { /* AIPS1 */
79*4882a593Smuzhiyun			compatible = "fsl,aips-bus", "simple-bus";
80*4882a593Smuzhiyun			#address-cells = <1>;
81*4882a593Smuzhiyun			#size-cells = <1>;
82*4882a593Smuzhiyun			reg = <0x43f00000 0x100000>;
83*4882a593Smuzhiyun			ranges;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun			aips1: bridge@43f00000 {
86*4882a593Smuzhiyun				compatible = "fsl,imx25-aips";
87*4882a593Smuzhiyun				reg = <0x43f00000 0x4000>;
88*4882a593Smuzhiyun			};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun			i2c1: i2c@43f80000 {
91*4882a593Smuzhiyun				#address-cells = <1>;
92*4882a593Smuzhiyun				#size-cells = <0>;
93*4882a593Smuzhiyun				compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
94*4882a593Smuzhiyun				reg = <0x43f80000 0x4000>;
95*4882a593Smuzhiyun				clocks = <&clks 48>;
96*4882a593Smuzhiyun				clock-names = "";
97*4882a593Smuzhiyun				interrupts = <3>;
98*4882a593Smuzhiyun				status = "disabled";
99*4882a593Smuzhiyun			};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun			i2c3: i2c@43f84000 {
102*4882a593Smuzhiyun				#address-cells = <1>;
103*4882a593Smuzhiyun				#size-cells = <0>;
104*4882a593Smuzhiyun				compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
105*4882a593Smuzhiyun				reg = <0x43f84000 0x4000>;
106*4882a593Smuzhiyun				clocks = <&clks 48>;
107*4882a593Smuzhiyun				clock-names = "";
108*4882a593Smuzhiyun				interrupts = <10>;
109*4882a593Smuzhiyun				status = "disabled";
110*4882a593Smuzhiyun			};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun			can1: can@43f88000 {
113*4882a593Smuzhiyun				compatible = "fsl,imx25-flexcan";
114*4882a593Smuzhiyun				reg = <0x43f88000 0x4000>;
115*4882a593Smuzhiyun				interrupts = <43>;
116*4882a593Smuzhiyun				clocks = <&clks 75>, <&clks 75>;
117*4882a593Smuzhiyun				clock-names = "ipg", "per";
118*4882a593Smuzhiyun				status = "disabled";
119*4882a593Smuzhiyun			};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun			can2: can@43f8c000 {
122*4882a593Smuzhiyun				compatible = "fsl,imx25-flexcan";
123*4882a593Smuzhiyun				reg = <0x43f8c000 0x4000>;
124*4882a593Smuzhiyun				interrupts = <44>;
125*4882a593Smuzhiyun				clocks = <&clks 76>, <&clks 76>;
126*4882a593Smuzhiyun				clock-names = "ipg", "per";
127*4882a593Smuzhiyun				status = "disabled";
128*4882a593Smuzhiyun			};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun			uart1: serial@43f90000 {
131*4882a593Smuzhiyun				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
132*4882a593Smuzhiyun				reg = <0x43f90000 0x4000>;
133*4882a593Smuzhiyun				interrupts = <45>;
134*4882a593Smuzhiyun				clocks = <&clks 120>, <&clks 57>;
135*4882a593Smuzhiyun				clock-names = "ipg", "per";
136*4882a593Smuzhiyun				status = "disabled";
137*4882a593Smuzhiyun			};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun			uart2: serial@43f94000 {
140*4882a593Smuzhiyun				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
141*4882a593Smuzhiyun				reg = <0x43f94000 0x4000>;
142*4882a593Smuzhiyun				interrupts = <32>;
143*4882a593Smuzhiyun				clocks = <&clks 121>, <&clks 57>;
144*4882a593Smuzhiyun				clock-names = "ipg", "per";
145*4882a593Smuzhiyun				status = "disabled";
146*4882a593Smuzhiyun			};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun			i2c2: i2c@43f98000 {
149*4882a593Smuzhiyun				#address-cells = <1>;
150*4882a593Smuzhiyun				#size-cells = <0>;
151*4882a593Smuzhiyun				compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
152*4882a593Smuzhiyun				reg = <0x43f98000 0x4000>;
153*4882a593Smuzhiyun				clocks = <&clks 48>;
154*4882a593Smuzhiyun				clock-names = "";
155*4882a593Smuzhiyun				interrupts = <4>;
156*4882a593Smuzhiyun				status = "disabled";
157*4882a593Smuzhiyun			};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun			owire@43f9c000 {
160*4882a593Smuzhiyun				#address-cells = <1>;
161*4882a593Smuzhiyun				#size-cells = <0>;
162*4882a593Smuzhiyun				reg = <0x43f9c000 0x4000>;
163*4882a593Smuzhiyun				clocks = <&clks 51>;
164*4882a593Smuzhiyun				clock-names = "";
165*4882a593Smuzhiyun				interrupts = <2>;
166*4882a593Smuzhiyun				status = "disabled";
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			spi1: spi@43fa4000 {
170*4882a593Smuzhiyun				#address-cells = <1>;
171*4882a593Smuzhiyun				#size-cells = <0>;
172*4882a593Smuzhiyun				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
173*4882a593Smuzhiyun				reg = <0x43fa4000 0x4000>;
174*4882a593Smuzhiyun				clocks = <&clks 78>, <&clks 78>;
175*4882a593Smuzhiyun				clock-names = "ipg", "per";
176*4882a593Smuzhiyun				interrupts = <14>;
177*4882a593Smuzhiyun				status = "disabled";
178*4882a593Smuzhiyun			};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun			kpp: kpp@43fa8000 {
181*4882a593Smuzhiyun				#address-cells = <1>;
182*4882a593Smuzhiyun				#size-cells = <0>;
183*4882a593Smuzhiyun				compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
184*4882a593Smuzhiyun				reg = <0x43fa8000 0x4000>;
185*4882a593Smuzhiyun				clocks = <&clks 102>;
186*4882a593Smuzhiyun				clock-names = "";
187*4882a593Smuzhiyun				interrupts = <24>;
188*4882a593Smuzhiyun				status = "disabled";
189*4882a593Smuzhiyun			};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun			iomuxc: iomuxc@43fac000 {
192*4882a593Smuzhiyun				compatible = "fsl,imx25-iomuxc";
193*4882a593Smuzhiyun				reg = <0x43fac000 0x4000>;
194*4882a593Smuzhiyun			};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun			audmux: audmux@43fb0000 {
197*4882a593Smuzhiyun				compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
198*4882a593Smuzhiyun				reg = <0x43fb0000 0x4000>;
199*4882a593Smuzhiyun				status = "disabled";
200*4882a593Smuzhiyun			};
201*4882a593Smuzhiyun		};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun		spba@50000000 {
204*4882a593Smuzhiyun			compatible = "fsl,spba-bus", "simple-bus";
205*4882a593Smuzhiyun			#address-cells = <1>;
206*4882a593Smuzhiyun			#size-cells = <1>;
207*4882a593Smuzhiyun			reg = <0x50000000 0x40000>;
208*4882a593Smuzhiyun			ranges;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun			spi3: spi@50004000 {
211*4882a593Smuzhiyun				#address-cells = <1>;
212*4882a593Smuzhiyun				#size-cells = <0>;
213*4882a593Smuzhiyun				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
214*4882a593Smuzhiyun				reg = <0x50004000 0x4000>;
215*4882a593Smuzhiyun				interrupts = <0>;
216*4882a593Smuzhiyun				clocks = <&clks 80>, <&clks 80>;
217*4882a593Smuzhiyun				clock-names = "ipg", "per";
218*4882a593Smuzhiyun				status = "disabled";
219*4882a593Smuzhiyun			};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun			uart4: serial@50008000 {
222*4882a593Smuzhiyun				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
223*4882a593Smuzhiyun				reg = <0x50008000 0x4000>;
224*4882a593Smuzhiyun				interrupts = <5>;
225*4882a593Smuzhiyun				clocks = <&clks 123>, <&clks 57>;
226*4882a593Smuzhiyun				clock-names = "ipg", "per";
227*4882a593Smuzhiyun				status = "disabled";
228*4882a593Smuzhiyun			};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun			uart3: serial@5000c000 {
231*4882a593Smuzhiyun				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
232*4882a593Smuzhiyun				reg = <0x5000c000 0x4000>;
233*4882a593Smuzhiyun				interrupts = <18>;
234*4882a593Smuzhiyun				clocks = <&clks 122>, <&clks 57>;
235*4882a593Smuzhiyun				clock-names = "ipg", "per";
236*4882a593Smuzhiyun				status = "disabled";
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun			spi2: spi@50010000 {
240*4882a593Smuzhiyun				#address-cells = <1>;
241*4882a593Smuzhiyun				#size-cells = <0>;
242*4882a593Smuzhiyun				compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
243*4882a593Smuzhiyun				reg = <0x50010000 0x4000>;
244*4882a593Smuzhiyun				clocks = <&clks 79>, <&clks 79>;
245*4882a593Smuzhiyun				clock-names = "ipg", "per";
246*4882a593Smuzhiyun				interrupts = <13>;
247*4882a593Smuzhiyun				status = "disabled";
248*4882a593Smuzhiyun			};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun			ssi2: ssi@50014000 {
251*4882a593Smuzhiyun				#sound-dai-cells = <0>;
252*4882a593Smuzhiyun				compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
253*4882a593Smuzhiyun				reg = <0x50014000 0x4000>;
254*4882a593Smuzhiyun				interrupts = <11>;
255*4882a593Smuzhiyun				clocks = <&clks 118>;
256*4882a593Smuzhiyun				clock-names = "ipg";
257*4882a593Smuzhiyun				dmas = <&sdma 24 1 0>,
258*4882a593Smuzhiyun				       <&sdma 25 1 0>;
259*4882a593Smuzhiyun				dma-names = "rx", "tx";
260*4882a593Smuzhiyun				fsl,fifo-depth = <15>;
261*4882a593Smuzhiyun				status = "disabled";
262*4882a593Smuzhiyun			};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun			esai@50018000 {
265*4882a593Smuzhiyun				reg = <0x50018000 0x4000>;
266*4882a593Smuzhiyun				interrupts = <7>;
267*4882a593Smuzhiyun			};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun			uart5: serial@5002c000 {
270*4882a593Smuzhiyun				compatible = "fsl,imx25-uart", "fsl,imx21-uart";
271*4882a593Smuzhiyun				reg = <0x5002c000 0x4000>;
272*4882a593Smuzhiyun				interrupts = <40>;
273*4882a593Smuzhiyun				clocks = <&clks 124>, <&clks 57>;
274*4882a593Smuzhiyun				clock-names = "ipg", "per";
275*4882a593Smuzhiyun				status = "disabled";
276*4882a593Smuzhiyun			};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun			tscadc: tscadc@50030000 {
279*4882a593Smuzhiyun				compatible = "fsl,imx25-tsadc";
280*4882a593Smuzhiyun				reg = <0x50030000 0xc>;
281*4882a593Smuzhiyun				interrupts = <46>;
282*4882a593Smuzhiyun				clocks = <&clks 119>;
283*4882a593Smuzhiyun				clock-names = "ipg";
284*4882a593Smuzhiyun				interrupt-controller;
285*4882a593Smuzhiyun				#interrupt-cells = <1>;
286*4882a593Smuzhiyun				#address-cells = <1>;
287*4882a593Smuzhiyun				#size-cells = <1>;
288*4882a593Smuzhiyun				status = "disabled";
289*4882a593Smuzhiyun				ranges;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun				adc: adc@50030800 {
292*4882a593Smuzhiyun					compatible = "fsl,imx25-gcq";
293*4882a593Smuzhiyun					reg = <0x50030800 0x60>;
294*4882a593Smuzhiyun					interrupt-parent = <&tscadc>;
295*4882a593Smuzhiyun					interrupts = <1>;
296*4882a593Smuzhiyun					#address-cells = <1>;
297*4882a593Smuzhiyun					#size-cells = <0>;
298*4882a593Smuzhiyun					status = "disabled";
299*4882a593Smuzhiyun				};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun				tsc: tcq@50030400 {
302*4882a593Smuzhiyun					compatible = "fsl,imx25-tcq";
303*4882a593Smuzhiyun					reg = <0x50030400 0x60>;
304*4882a593Smuzhiyun					interrupt-parent = <&tscadc>;
305*4882a593Smuzhiyun					interrupts = <0>;
306*4882a593Smuzhiyun					fsl,wires = <4>;
307*4882a593Smuzhiyun					status = "disabled";
308*4882a593Smuzhiyun				};
309*4882a593Smuzhiyun			};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun			ssi1: ssi@50034000 {
312*4882a593Smuzhiyun				#sound-dai-cells = <0>;
313*4882a593Smuzhiyun				compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
314*4882a593Smuzhiyun				reg = <0x50034000 0x4000>;
315*4882a593Smuzhiyun				interrupts = <12>;
316*4882a593Smuzhiyun				clocks = <&clks 117>;
317*4882a593Smuzhiyun				clock-names = "ipg";
318*4882a593Smuzhiyun				dmas = <&sdma 28 1 0>,
319*4882a593Smuzhiyun				       <&sdma 29 1 0>;
320*4882a593Smuzhiyun				dma-names = "rx", "tx";
321*4882a593Smuzhiyun				fsl,fifo-depth = <15>;
322*4882a593Smuzhiyun				status = "disabled";
323*4882a593Smuzhiyun			};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun			fec: ethernet@50038000 {
326*4882a593Smuzhiyun				compatible = "fsl,imx25-fec";
327*4882a593Smuzhiyun				reg = <0x50038000 0x4000>;
328*4882a593Smuzhiyun				interrupts = <57>;
329*4882a593Smuzhiyun				clocks = <&clks 88>, <&clks 65>;
330*4882a593Smuzhiyun				clock-names = "ipg", "ahb";
331*4882a593Smuzhiyun				status = "disabled";
332*4882a593Smuzhiyun			};
333*4882a593Smuzhiyun		};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun		bus@53f00000 { /* AIPS2 */
336*4882a593Smuzhiyun			compatible = "fsl,aips-bus", "simple-bus";
337*4882a593Smuzhiyun			#address-cells = <1>;
338*4882a593Smuzhiyun			#size-cells = <1>;
339*4882a593Smuzhiyun			reg = <0x53f00000 0x100000>;
340*4882a593Smuzhiyun			ranges;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun			aips2: bridge@53f00000 {
343*4882a593Smuzhiyun				compatible = "fsl,imx25-aips";
344*4882a593Smuzhiyun				reg = <0x53f00000 0x4000>;
345*4882a593Smuzhiyun			};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun			clks: ccm@53f80000 {
348*4882a593Smuzhiyun				compatible = "fsl,imx25-ccm";
349*4882a593Smuzhiyun				reg = <0x53f80000 0x4000>;
350*4882a593Smuzhiyun				interrupts = <31>;
351*4882a593Smuzhiyun				#clock-cells = <1>;
352*4882a593Smuzhiyun			};
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun			gpt4: timer@53f84000 {
355*4882a593Smuzhiyun				compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
356*4882a593Smuzhiyun				reg = <0x53f84000 0x4000>;
357*4882a593Smuzhiyun				clocks = <&clks 95>, <&clks 47>;
358*4882a593Smuzhiyun				clock-names = "ipg", "per";
359*4882a593Smuzhiyun				interrupts = <1>;
360*4882a593Smuzhiyun			};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun			gpt3: timer@53f88000 {
363*4882a593Smuzhiyun				compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
364*4882a593Smuzhiyun				reg = <0x53f88000 0x4000>;
365*4882a593Smuzhiyun				clocks = <&clks 94>, <&clks 47>;
366*4882a593Smuzhiyun				clock-names = "ipg", "per";
367*4882a593Smuzhiyun				interrupts = <29>;
368*4882a593Smuzhiyun			};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun			gpt2: timer@53f8c000 {
371*4882a593Smuzhiyun				compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
372*4882a593Smuzhiyun				reg = <0x53f8c000 0x4000>;
373*4882a593Smuzhiyun				clocks = <&clks 93>, <&clks 47>;
374*4882a593Smuzhiyun				clock-names = "ipg", "per";
375*4882a593Smuzhiyun				interrupts = <53>;
376*4882a593Smuzhiyun			};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun			gpt1: timer@53f90000 {
379*4882a593Smuzhiyun				compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
380*4882a593Smuzhiyun				reg = <0x53f90000 0x4000>;
381*4882a593Smuzhiyun				clocks = <&clks 92>, <&clks 47>;
382*4882a593Smuzhiyun				clock-names = "ipg", "per";
383*4882a593Smuzhiyun				interrupts = <54>;
384*4882a593Smuzhiyun			};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun			epit1: timer@53f94000 {
387*4882a593Smuzhiyun				compatible = "fsl,imx25-epit";
388*4882a593Smuzhiyun				reg = <0x53f94000 0x4000>;
389*4882a593Smuzhiyun				clocks = <&clks 83>, <&clks 43>;
390*4882a593Smuzhiyun				clock-names = "ipg", "per";
391*4882a593Smuzhiyun				interrupts = <28>;
392*4882a593Smuzhiyun			};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun			epit2: timer@53f98000 {
395*4882a593Smuzhiyun				compatible = "fsl,imx25-epit";
396*4882a593Smuzhiyun				reg = <0x53f98000 0x4000>;
397*4882a593Smuzhiyun				clocks = <&clks 84>, <&clks 43>;
398*4882a593Smuzhiyun				clock-names = "ipg", "per";
399*4882a593Smuzhiyun				interrupts = <27>;
400*4882a593Smuzhiyun			};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun			gpio4: gpio@53f9c000 {
403*4882a593Smuzhiyun				compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
404*4882a593Smuzhiyun				reg = <0x53f9c000 0x4000>;
405*4882a593Smuzhiyun				interrupts = <23>;
406*4882a593Smuzhiyun				gpio-controller;
407*4882a593Smuzhiyun				#gpio-cells = <2>;
408*4882a593Smuzhiyun				interrupt-controller;
409*4882a593Smuzhiyun				#interrupt-cells = <2>;
410*4882a593Smuzhiyun			};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun			pwm2: pwm@53fa0000 {
413*4882a593Smuzhiyun				compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
414*4882a593Smuzhiyun				#pwm-cells = <3>;
415*4882a593Smuzhiyun				reg = <0x53fa0000 0x4000>;
416*4882a593Smuzhiyun				clocks = <&clks 106>, <&clks 52>;
417*4882a593Smuzhiyun				clock-names = "ipg", "per";
418*4882a593Smuzhiyun				interrupts = <36>;
419*4882a593Smuzhiyun			};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun			gpio3: gpio@53fa4000 {
422*4882a593Smuzhiyun				compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
423*4882a593Smuzhiyun				reg = <0x53fa4000 0x4000>;
424*4882a593Smuzhiyun				interrupts = <16>;
425*4882a593Smuzhiyun				gpio-controller;
426*4882a593Smuzhiyun				#gpio-cells = <2>;
427*4882a593Smuzhiyun				interrupt-controller;
428*4882a593Smuzhiyun				#interrupt-cells = <2>;
429*4882a593Smuzhiyun			};
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun			pwm3: pwm@53fa8000 {
432*4882a593Smuzhiyun				compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
433*4882a593Smuzhiyun				#pwm-cells = <3>;
434*4882a593Smuzhiyun				reg = <0x53fa8000 0x4000>;
435*4882a593Smuzhiyun				clocks = <&clks 107>, <&clks 52>;
436*4882a593Smuzhiyun				clock-names = "ipg", "per";
437*4882a593Smuzhiyun				interrupts = <41>;
438*4882a593Smuzhiyun			};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun			scc: crypto@53fac000 {
441*4882a593Smuzhiyun				compatible = "fsl,imx25-scc";
442*4882a593Smuzhiyun				reg = <0x53fac000 0x4000>;
443*4882a593Smuzhiyun				clocks = <&clks 111>;
444*4882a593Smuzhiyun				clock-names = "ipg";
445*4882a593Smuzhiyun				interrupts = <49>, <50>;
446*4882a593Smuzhiyun				interrupt-names = "scm", "smn";
447*4882a593Smuzhiyun			};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun			rngb: rngb@53fb0000 {
450*4882a593Smuzhiyun				compatible = "fsl,imx25-rngb";
451*4882a593Smuzhiyun				reg = <0x53fb0000 0x4000>;
452*4882a593Smuzhiyun				clocks = <&clks 109>;
453*4882a593Smuzhiyun				interrupts = <22>;
454*4882a593Smuzhiyun			};
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun			esdhc1: mmc@53fb4000 {
457*4882a593Smuzhiyun				compatible = "fsl,imx25-esdhc";
458*4882a593Smuzhiyun				reg = <0x53fb4000 0x4000>;
459*4882a593Smuzhiyun				interrupts = <9>;
460*4882a593Smuzhiyun				clocks = <&clks 86>, <&clks 63>, <&clks 45>;
461*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "per";
462*4882a593Smuzhiyun				status = "disabled";
463*4882a593Smuzhiyun			};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun			esdhc2: mmc@53fb8000 {
466*4882a593Smuzhiyun				compatible = "fsl,imx25-esdhc";
467*4882a593Smuzhiyun				reg = <0x53fb8000 0x4000>;
468*4882a593Smuzhiyun				interrupts = <8>;
469*4882a593Smuzhiyun				clocks = <&clks 87>, <&clks 64>, <&clks 46>;
470*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "per";
471*4882a593Smuzhiyun				status = "disabled";
472*4882a593Smuzhiyun			};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun			lcdc: lcdc@53fbc000 {
475*4882a593Smuzhiyun				compatible = "fsl,imx25-fb", "fsl,imx21-fb";
476*4882a593Smuzhiyun				reg = <0x53fbc000 0x4000>;
477*4882a593Smuzhiyun				interrupts = <39>;
478*4882a593Smuzhiyun				clocks = <&clks 103>, <&clks 66>, <&clks 49>;
479*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "per";
480*4882a593Smuzhiyun				status = "disabled";
481*4882a593Smuzhiyun			};
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun			slcdc@53fc0000 {
484*4882a593Smuzhiyun				reg = <0x53fc0000 0x4000>;
485*4882a593Smuzhiyun				interrupts = <38>;
486*4882a593Smuzhiyun				status = "disabled";
487*4882a593Smuzhiyun			};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun			pwm4: pwm@53fc8000 {
490*4882a593Smuzhiyun				compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
491*4882a593Smuzhiyun				#pwm-cells = <3>;
492*4882a593Smuzhiyun				reg = <0x53fc8000 0x4000>;
493*4882a593Smuzhiyun				clocks = <&clks 108>, <&clks 52>;
494*4882a593Smuzhiyun				clock-names = "ipg", "per";
495*4882a593Smuzhiyun				interrupts = <42>;
496*4882a593Smuzhiyun			};
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun			gpio1: gpio@53fcc000 {
499*4882a593Smuzhiyun				compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
500*4882a593Smuzhiyun				reg = <0x53fcc000 0x4000>;
501*4882a593Smuzhiyun				interrupts = <52>;
502*4882a593Smuzhiyun				gpio-controller;
503*4882a593Smuzhiyun				#gpio-cells = <2>;
504*4882a593Smuzhiyun				interrupt-controller;
505*4882a593Smuzhiyun				#interrupt-cells = <2>;
506*4882a593Smuzhiyun			};
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun			gpio2: gpio@53fd0000 {
509*4882a593Smuzhiyun				compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
510*4882a593Smuzhiyun				reg = <0x53fd0000 0x4000>;
511*4882a593Smuzhiyun				interrupts = <51>;
512*4882a593Smuzhiyun				gpio-controller;
513*4882a593Smuzhiyun				#gpio-cells = <2>;
514*4882a593Smuzhiyun				interrupt-controller;
515*4882a593Smuzhiyun				#interrupt-cells = <2>;
516*4882a593Smuzhiyun			};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun			sdma: sdma@53fd4000 {
519*4882a593Smuzhiyun				compatible = "fsl,imx25-sdma";
520*4882a593Smuzhiyun				reg = <0x53fd4000 0x4000>;
521*4882a593Smuzhiyun				clocks = <&clks 112>, <&clks 68>;
522*4882a593Smuzhiyun				clock-names = "ipg", "ahb";
523*4882a593Smuzhiyun				#dma-cells = <3>;
524*4882a593Smuzhiyun				interrupts = <34>;
525*4882a593Smuzhiyun				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
526*4882a593Smuzhiyun			};
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun			wdog@53fdc000 {
529*4882a593Smuzhiyun				compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
530*4882a593Smuzhiyun				reg = <0x53fdc000 0x4000>;
531*4882a593Smuzhiyun				clocks = <&clks 126>;
532*4882a593Smuzhiyun				clock-names = "";
533*4882a593Smuzhiyun				interrupts = <55>;
534*4882a593Smuzhiyun			};
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun			pwm1: pwm@53fe0000 {
537*4882a593Smuzhiyun				compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
538*4882a593Smuzhiyun				#pwm-cells = <3>;
539*4882a593Smuzhiyun				reg = <0x53fe0000 0x4000>;
540*4882a593Smuzhiyun				clocks = <&clks 105>, <&clks 52>;
541*4882a593Smuzhiyun				clock-names = "ipg", "per";
542*4882a593Smuzhiyun				interrupts = <26>;
543*4882a593Smuzhiyun			};
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun			iim: efuse@53ff0000 {
546*4882a593Smuzhiyun				compatible = "fsl,imx25-iim", "fsl,imx27-iim";
547*4882a593Smuzhiyun				reg = <0x53ff0000 0x4000>;
548*4882a593Smuzhiyun				interrupts = <19>;
549*4882a593Smuzhiyun				clocks = <&clks 99>;
550*4882a593Smuzhiyun			};
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun			usbotg: usb@53ff4000 {
553*4882a593Smuzhiyun				compatible = "fsl,imx25-usb", "fsl,imx27-usb";
554*4882a593Smuzhiyun				reg = <0x53ff4000 0x0200>;
555*4882a593Smuzhiyun				interrupts = <37>;
556*4882a593Smuzhiyun				clocks = <&clks 9>, <&clks 70>, <&clks 8>;
557*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "per";
558*4882a593Smuzhiyun				fsl,usbmisc = <&usbmisc 0>;
559*4882a593Smuzhiyun				fsl,usbphy = <&usbphy0>;
560*4882a593Smuzhiyun				phy_type = "utmi";
561*4882a593Smuzhiyun				dr_mode = "otg";
562*4882a593Smuzhiyun				status = "disabled";
563*4882a593Smuzhiyun			};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun			usbhost1: usb@53ff4400 {
566*4882a593Smuzhiyun				compatible = "fsl,imx25-usb", "fsl,imx27-usb";
567*4882a593Smuzhiyun				reg = <0x53ff4400 0x0200>;
568*4882a593Smuzhiyun				interrupts = <35>;
569*4882a593Smuzhiyun				clocks = <&clks 9>, <&clks 70>, <&clks 8>;
570*4882a593Smuzhiyun				clock-names = "ipg", "ahb", "per";
571*4882a593Smuzhiyun				fsl,usbmisc = <&usbmisc 1>;
572*4882a593Smuzhiyun				fsl,usbphy = <&usbphy1>;
573*4882a593Smuzhiyun				maximum-speed = "full-speed";
574*4882a593Smuzhiyun				phy_type = "serial";
575*4882a593Smuzhiyun				dr_mode = "host";
576*4882a593Smuzhiyun				status = "disabled";
577*4882a593Smuzhiyun			};
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun			usbmisc: usbmisc@53ff4600 {
580*4882a593Smuzhiyun				#index-cells = <1>;
581*4882a593Smuzhiyun				compatible = "fsl,imx25-usbmisc";
582*4882a593Smuzhiyun				reg = <0x53ff4600 0x00f>;
583*4882a593Smuzhiyun			};
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun			dryice@53ffc000 {
586*4882a593Smuzhiyun				compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
587*4882a593Smuzhiyun				reg = <0x53ffc000 0x4000>;
588*4882a593Smuzhiyun				clocks = <&clks 81>;
589*4882a593Smuzhiyun				clock-names = "ipg";
590*4882a593Smuzhiyun				interrupts = <25 56>;
591*4882a593Smuzhiyun			};
592*4882a593Smuzhiyun		};
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun		iram: sram@78000000 {
595*4882a593Smuzhiyun			compatible = "mmio-sram";
596*4882a593Smuzhiyun			reg = <0x78000000 0x20000>;
597*4882a593Smuzhiyun		};
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun		emi@80000000 {
600*4882a593Smuzhiyun			compatible = "fsl,emi-bus", "simple-bus";
601*4882a593Smuzhiyun			#address-cells = <1>;
602*4882a593Smuzhiyun			#size-cells = <1>;
603*4882a593Smuzhiyun			reg = <0x80000000 0x3b002000>;
604*4882a593Smuzhiyun			ranges;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun			nfc: nand@bb000000 {
607*4882a593Smuzhiyun				#address-cells = <1>;
608*4882a593Smuzhiyun				#size-cells = <1>;
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun				compatible = "fsl,imx25-nand";
611*4882a593Smuzhiyun				reg = <0xbb000000 0x2000>;
612*4882a593Smuzhiyun				clocks = <&clks 50>;
613*4882a593Smuzhiyun				clock-names = "";
614*4882a593Smuzhiyun				interrupts = <33>;
615*4882a593Smuzhiyun				status = "disabled";
616*4882a593Smuzhiyun			};
617*4882a593Smuzhiyun		};
618*4882a593Smuzhiyun	};
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun	usbphy {
621*4882a593Smuzhiyun		compatible = "simple-bus";
622*4882a593Smuzhiyun		#address-cells = <1>;
623*4882a593Smuzhiyun		#size-cells = <0>;
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun		usbphy0: usb-phy@0 {
626*4882a593Smuzhiyun			reg = <0>;
627*4882a593Smuzhiyun			compatible = "usb-nop-xceiv";
628*4882a593Smuzhiyun			#phy-cells = <0>;
629*4882a593Smuzhiyun		};
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun		usbphy1: usb-phy@1 {
632*4882a593Smuzhiyun			reg = <1>;
633*4882a593Smuzhiyun			compatible = "usb-nop-xceiv";
634*4882a593Smuzhiyun			#phy-cells = <0>;
635*4882a593Smuzhiyun		};
636*4882a593Smuzhiyun	};
637*4882a593Smuzhiyun};
638