Lines Matching +full:0 +full:x53f80000
28 u32 cgr0; /* Clock Gating Control 0 */
34 u32 dcvr0; /* DPTC Comparator Value 0 */
38 u32 ltr0; /* Load Tracking 0 */
42 u32 ltbr0; /* Load Tracking Buffer 0 */
44 u32 pcmr0; /* Power Management Control 0 */
48 u32 lpimr0; /* Low Power Interrupt Mask 0 */
54 u32 ctl0; /* control 0 */
55 u32 cfg0; /* configuration 0 */
105 u32 res1[0x1f1];
107 u32 fuse_regs[0x20];
108 u32 fuse_rsvd[0xe0];
115 u32 fuse16_25[0xa];
120 u32 fuse0_21[0x16];
201 u32 cscr0u; /* Chip Select 0 Upper Register */
202 u32 cscr0l; /* Chip Select 0 Lower Register */
203 u32 cscr0a; /* Chip Select 0 Addition Register */
231 u32 wcfg0; /* Watermark Configuration Register 0 */
240 u32 scfg0; /* Snooping Configuration Register 0 */
243 u32 ssr0; /* Snooping Status Register 0 */
290 #define IMX_AIPS1_BASE (0x43F00000)
291 #define IMX_MAX_BASE (0x43F04000)
292 #define IMX_CLKCTL_BASE (0x43F08000)
293 #define IMX_ETB_SLOT4_BASE (0x43F0C000)
294 #define IMX_ETB_SLOT5_BASE (0x43F10000)
295 #define IMX_ECT_CTIO_BASE (0x43F18000)
296 #define I2C1_BASE_ADDR (0x43F80000)
297 #define I2C3_BASE_ADDR (0x43F84000)
298 #define IMX_CAN1_BASE (0x43F88000)
299 #define IMX_CAN2_BASE (0x43F8C000)
300 #define UART1_BASE (0x43F90000)
301 #define UART2_BASE (0x43F94000)
302 #define I2C2_BASE_ADDR (0x43F98000)
303 #define IMX_OWIRE_BASE (0x43F9C000)
304 #define IMX_CSPI1_BASE (0x43FA4000)
305 #define IMX_KPP_BASE (0x43FA8000)
306 #define IMX_IOPADMUX_BASE (0x43FAC000)
308 #define IMX_IOPADCTL_BASE (0x43FAC22C)
309 #define IMX_IOPADGRPCTL_BASE (0x43FAC418)
310 #define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
311 #define IMX_AUDMUX_BASE (0x43FB0000)
312 #define IMX_ECT_IP1_BASE (0x43FB8000)
313 #define IMX_ECT_IP2_BASE (0x43FBC000)
316 #define IMX_SPBA_BASE (0x50000000)
317 #define IMX_CSPI3_BASE (0x50004000)
318 #define UART4_BASE (0x50008000)
319 #define UART3_BASE (0x5000C000)
320 #define IMX_CSPI2_BASE (0x50010000)
321 #define IMX_SSI2_BASE (0x50014000)
322 #define IMX_ESAI_BASE (0x50018000)
323 #define IMX_ATA_DMA_BASE (0x50020000)
324 #define IMX_SIM1_BASE (0x50024000)
325 #define IMX_SIM2_BASE (0x50028000)
326 #define UART5_BASE (0x5002C000)
327 #define IMX_TSC_BASE (0x50030000)
328 #define IMX_SSI1_BASE (0x50034000)
329 #define IMX_FEC_BASE (0x50038000)
330 #define IMX_SPBA_CTRL_BASE (0x5003C000)
333 #define IMX_AIPS2_BASE (0x53F00000)
334 #define IMX_CCM_BASE (0x53F80000)
335 #define IMX_GPT4_BASE (0x53F84000)
336 #define IMX_GPT3_BASE (0x53F88000)
337 #define IMX_GPT2_BASE (0x53F8C000)
338 #define IMX_GPT1_BASE (0x53F90000)
339 #define IMX_EPIT1_BASE (0x53F94000)
340 #define IMX_EPIT2_BASE (0x53F98000)
341 #define IMX_GPIO4_BASE (0x53F9C000)
342 #define IMX_PWM2_BASE (0x53FA0000)
343 #define IMX_GPIO3_BASE (0x53FA4000)
344 #define IMX_PWM3_BASE (0x53FA8000)
345 #define IMX_SCC_BASE (0x53FAC000)
346 #define IMX_SCM_BASE (0x53FAE000)
347 #define IMX_SMN_BASE (0x53FAF000)
348 #define IMX_RNGD_BASE (0x53FB0000)
349 #define IMX_MMC_SDHC1_BASE (0x53FB4000)
350 #define IMX_MMC_SDHC2_BASE (0x53FB8000)
351 #define IMX_LCDC_BASE (0x53FBC000)
352 #define IMX_SLCDC_BASE (0x53FC0000)
353 #define IMX_PWM4_BASE (0x53FC8000)
354 #define IMX_GPIO1_BASE (0x53FCC000)
355 #define IMX_GPIO2_BASE (0x53FD0000)
356 #define IMX_SDMA_BASE (0x53FD4000)
357 #define IMX_WDT_BASE (0x53FDC000)
358 #define IMX_PWM1_BASE (0x53FE0000)
359 #define IMX_RTIC_BASE (0x53FEC000)
360 #define IMX_IIM_BASE (0x53FF0000)
362 #define IMX_USB_BASE (0x53FF4000)
363 #define IMX_USB_PORT_OFFSET 0x200
364 #define IMX_CSI_BASE (0x53FF8000)
365 #define IMX_DRYICE_BASE (0x53FFC000)
367 #define IMX_ARM926_ROMPATCH (0x60000000)
368 #define IMX_ARM926_ASIC (0x68000000)
371 #define IMX_RAM_BASE (0x78000000)
375 #define IMX_SDRAM_BANK0_BASE (0x80000000)
376 #define IMX_SDRAM_BANK1_BASE (0x90000000)
378 #define IMX_WEIM_CS0 (0xA0000000)
379 #define IMX_WEIM_CS1 (0xA8000000)
380 #define IMX_WEIM_CS2 (0xB0000000)
381 #define IMX_WEIM_CS3 (0xB2000000)
382 #define IMX_WEIM_CS4 (0xB4000000)
383 #define IMX_ESDRAMC_BASE (0xB8001000)
384 #define IMX_WEIM_CTRL_BASE (0xB8002000)
385 #define IMX_M3IF_CTRL_BASE (0xB8003000)
386 #define IMX_EMI_CTRL_BASE (0xB8004000)
389 #define IMX_NFC_BASE (0xBB000000)
394 #define CCM_PLL_MFI_MASK 0xf
395 #define CCM_PLL_MFN_SHIFT 0
396 #define CCM_PLL_MFN_MASK 0x3ff
398 #define CCM_PLL_MFD_MASK 0x3ff
400 #define CCM_PLL_PD_MASK 0xf
409 #define CCM_PERCLK_MASK 0x3f
416 #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
421 #define ESDCTL_DSIZ_16_UPPER (0 << 16)
424 #define ESDCTL_COL8 (0 << 20)
427 #define ESDCTL_ROW11 (0 << 24)
433 #define ESDCTL_SMODE_NORMAL (0 << 28)
440 #define ESDCFG_TRC(x) (((x) & 0xf) << 0)
441 #define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
442 #define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
443 #define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
444 #define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
446 #define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
447 #define ESDCFG_TRP(x) (((x) & 0x3) << 18)
449 #define ESDCFG_TXP(x) (((x) & 0x3) << 21)
466 #define WCR_WDE 0x04
467 #define WSR_UNLOCK1 0x5555
468 #define WSR_UNLOCK2 0xAAAA
471 #define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0)
474 #define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0)
482 (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
488 (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
495 (age) << 2 | (cnc2) << 1 | (fce) << 0)
507 #define MXC_CSPICTRL_EN (1 << 0)
515 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
516 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
517 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
520 #define MXC_CSPICTRL_MAXBITS 0xfff