1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/clock/imx25-clock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Clock bindings for Freescale i.MX25 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Sascha Hauer <s.hauer@pengutronix.de> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The clock consumer should specify the desired clock by having the clock 14*4882a593Smuzhiyun ID in its "clocks" phandle cell. The following is a full list of i.MX25 15*4882a593Smuzhiyun clocks and IDs. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun Clock ID 18*4882a593Smuzhiyun -------------------------- 19*4882a593Smuzhiyun dummy 0 20*4882a593Smuzhiyun osc 1 21*4882a593Smuzhiyun mpll 2 22*4882a593Smuzhiyun upll 3 23*4882a593Smuzhiyun mpll_cpu_3_4 4 24*4882a593Smuzhiyun cpu_sel 5 25*4882a593Smuzhiyun cpu 6 26*4882a593Smuzhiyun ahb 7 27*4882a593Smuzhiyun usb_div 8 28*4882a593Smuzhiyun ipg 9 29*4882a593Smuzhiyun per0_sel 10 30*4882a593Smuzhiyun per1_sel 11 31*4882a593Smuzhiyun per2_sel 12 32*4882a593Smuzhiyun per3_sel 13 33*4882a593Smuzhiyun per4_sel 14 34*4882a593Smuzhiyun per5_sel 15 35*4882a593Smuzhiyun per6_sel 16 36*4882a593Smuzhiyun per7_sel 17 37*4882a593Smuzhiyun per8_sel 18 38*4882a593Smuzhiyun per9_sel 19 39*4882a593Smuzhiyun per10_sel 20 40*4882a593Smuzhiyun per11_sel 21 41*4882a593Smuzhiyun per12_sel 22 42*4882a593Smuzhiyun per13_sel 23 43*4882a593Smuzhiyun per14_sel 24 44*4882a593Smuzhiyun per15_sel 25 45*4882a593Smuzhiyun per0 26 46*4882a593Smuzhiyun per1 27 47*4882a593Smuzhiyun per2 28 48*4882a593Smuzhiyun per3 29 49*4882a593Smuzhiyun per4 30 50*4882a593Smuzhiyun per5 31 51*4882a593Smuzhiyun per6 32 52*4882a593Smuzhiyun per7 33 53*4882a593Smuzhiyun per8 34 54*4882a593Smuzhiyun per9 35 55*4882a593Smuzhiyun per10 36 56*4882a593Smuzhiyun per11 37 57*4882a593Smuzhiyun per12 38 58*4882a593Smuzhiyun per13 39 59*4882a593Smuzhiyun per14 40 60*4882a593Smuzhiyun per15 41 61*4882a593Smuzhiyun csi_ipg_per 42 62*4882a593Smuzhiyun epit_ipg_per 43 63*4882a593Smuzhiyun esai_ipg_per 44 64*4882a593Smuzhiyun esdhc1_ipg_per 45 65*4882a593Smuzhiyun esdhc2_ipg_per 46 66*4882a593Smuzhiyun gpt_ipg_per 47 67*4882a593Smuzhiyun i2c_ipg_per 48 68*4882a593Smuzhiyun lcdc_ipg_per 49 69*4882a593Smuzhiyun nfc_ipg_per 50 70*4882a593Smuzhiyun owire_ipg_per 51 71*4882a593Smuzhiyun pwm_ipg_per 52 72*4882a593Smuzhiyun sim1_ipg_per 53 73*4882a593Smuzhiyun sim2_ipg_per 54 74*4882a593Smuzhiyun ssi1_ipg_per 55 75*4882a593Smuzhiyun ssi2_ipg_per 56 76*4882a593Smuzhiyun uart_ipg_per 57 77*4882a593Smuzhiyun ata_ahb 58 78*4882a593Smuzhiyun reserved 59 79*4882a593Smuzhiyun csi_ahb 60 80*4882a593Smuzhiyun emi_ahb 61 81*4882a593Smuzhiyun esai_ahb 62 82*4882a593Smuzhiyun esdhc1_ahb 63 83*4882a593Smuzhiyun esdhc2_ahb 64 84*4882a593Smuzhiyun fec_ahb 65 85*4882a593Smuzhiyun lcdc_ahb 66 86*4882a593Smuzhiyun rtic_ahb 67 87*4882a593Smuzhiyun sdma_ahb 68 88*4882a593Smuzhiyun slcdc_ahb 69 89*4882a593Smuzhiyun usbotg_ahb 70 90*4882a593Smuzhiyun reserved 71 91*4882a593Smuzhiyun reserved 72 92*4882a593Smuzhiyun reserved 73 93*4882a593Smuzhiyun reserved 74 94*4882a593Smuzhiyun can1_ipg 75 95*4882a593Smuzhiyun can2_ipg 76 96*4882a593Smuzhiyun csi_ipg 77 97*4882a593Smuzhiyun cspi1_ipg 78 98*4882a593Smuzhiyun cspi2_ipg 79 99*4882a593Smuzhiyun cspi3_ipg 80 100*4882a593Smuzhiyun dryice_ipg 81 101*4882a593Smuzhiyun ect_ipg 82 102*4882a593Smuzhiyun epit1_ipg 83 103*4882a593Smuzhiyun epit2_ipg 84 104*4882a593Smuzhiyun reserved 85 105*4882a593Smuzhiyun esdhc1_ipg 86 106*4882a593Smuzhiyun esdhc2_ipg 87 107*4882a593Smuzhiyun fec_ipg 88 108*4882a593Smuzhiyun reserved 89 109*4882a593Smuzhiyun reserved 90 110*4882a593Smuzhiyun reserved 91 111*4882a593Smuzhiyun gpt1_ipg 92 112*4882a593Smuzhiyun gpt2_ipg 93 113*4882a593Smuzhiyun gpt3_ipg 94 114*4882a593Smuzhiyun gpt4_ipg 95 115*4882a593Smuzhiyun reserved 96 116*4882a593Smuzhiyun reserved 97 117*4882a593Smuzhiyun reserved 98 118*4882a593Smuzhiyun iim_ipg 99 119*4882a593Smuzhiyun reserved 100 120*4882a593Smuzhiyun reserved 101 121*4882a593Smuzhiyun kpp_ipg 102 122*4882a593Smuzhiyun lcdc_ipg 103 123*4882a593Smuzhiyun reserved 104 124*4882a593Smuzhiyun pwm1_ipg 105 125*4882a593Smuzhiyun pwm2_ipg 106 126*4882a593Smuzhiyun pwm3_ipg 107 127*4882a593Smuzhiyun pwm4_ipg 108 128*4882a593Smuzhiyun rngb_ipg 109 129*4882a593Smuzhiyun reserved 110 130*4882a593Smuzhiyun scc_ipg 111 131*4882a593Smuzhiyun sdma_ipg 112 132*4882a593Smuzhiyun sim1_ipg 113 133*4882a593Smuzhiyun sim2_ipg 114 134*4882a593Smuzhiyun slcdc_ipg 115 135*4882a593Smuzhiyun spba_ipg 116 136*4882a593Smuzhiyun ssi1_ipg 117 137*4882a593Smuzhiyun ssi2_ipg 118 138*4882a593Smuzhiyun tsc_ipg 119 139*4882a593Smuzhiyun uart1_ipg 120 140*4882a593Smuzhiyun uart2_ipg 121 141*4882a593Smuzhiyun uart3_ipg 122 142*4882a593Smuzhiyun uart4_ipg 123 143*4882a593Smuzhiyun uart5_ipg 124 144*4882a593Smuzhiyun reserved 125 145*4882a593Smuzhiyun wdt_ipg 126 146*4882a593Smuzhiyun cko_div 127 147*4882a593Smuzhiyun cko_sel 128 148*4882a593Smuzhiyun cko 129 149*4882a593Smuzhiyun 150*4882a593Smuzhiyunproperties: 151*4882a593Smuzhiyun compatible: 152*4882a593Smuzhiyun const: fsl,imx25-ccm 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun reg: 155*4882a593Smuzhiyun maxItems: 1 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun interrupts: 158*4882a593Smuzhiyun maxItems: 1 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun '#clock-cells': 161*4882a593Smuzhiyun const: 1 162*4882a593Smuzhiyun 163*4882a593Smuzhiyunrequired: 164*4882a593Smuzhiyun - compatible 165*4882a593Smuzhiyun - reg 166*4882a593Smuzhiyun - interrupts 167*4882a593Smuzhiyun - '#clock-cells' 168*4882a593Smuzhiyun 169*4882a593SmuzhiyunadditionalProperties: false 170*4882a593Smuzhiyun 171*4882a593Smuzhiyunexamples: 172*4882a593Smuzhiyun - | 173*4882a593Smuzhiyun clock-controller@53f80000 { 174*4882a593Smuzhiyun compatible = "fsl,imx25-ccm"; 175*4882a593Smuzhiyun reg = <0x53f80000 0x4000>; 176*4882a593Smuzhiyun interrupts = <31>; 177*4882a593Smuzhiyun #clock-cells = <1>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun serial@43f90000 { 181*4882a593Smuzhiyun compatible = "fsl,imx25-uart", "fsl,imx21-uart"; 182*4882a593Smuzhiyun reg = <0x43f90000 0x4000>; 183*4882a593Smuzhiyun interrupts = <45>; 184*4882a593Smuzhiyun clocks = <&clks 79>, <&clks 50>; 185*4882a593Smuzhiyun clock-names = "ipg", "per"; 186*4882a593Smuzhiyun }; 187