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/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dfb.c32 DEFINE_RES_MEM_NAMED(0x68008000u, 0x40, "vrfb-regs"),
33 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
34 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
35 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
36 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
40 DEFINE_RES_MEM_NAMED(0x6C000180u, 0xc0, "vrfb-regs"),
41 DEFINE_RES_MEM_NAMED(0x70000000u, 0x4000000, "vrfb-area-0"),
42 DEFINE_RES_MEM_NAMED(0x74000000u, 0x4000000, "vrfb-area-1"),
43 DEFINE_RES_MEM_NAMED(0x78000000u, 0x4000000, "vrfb-area-2"),
44 DEFINE_RES_MEM_NAMED(0x7c000000u, 0x4000000, "vrfb-area-3"),
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mtd/
H A Dti,am654-hbmc.txt23 reg = <0x0 0x47000000 0x0 0x100>;
31 mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */
37 reg = <0x0 0x47034000 0x0 0x100>,
38 <0x5 0x00000000 0x1 0x0000000>;
42 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
43 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
44 mux-controls = <&hbmc_mux 0>;
47 flash@0,0 {
49 reg = <0x0 0x0 0x4000000>;
H A Dqcom_nandc.txt35 - #size-cells: <0>
45 number (e.g., 0, 1, 2, etc.)
63 reg = <0x1ac00000 0x800>;
75 #size-cells = <0>;
77 nand@0 {
78 reg = <0>;
88 partition@0 {
90 reg = <0 0x58a0000>;
95 reg = <0x58a0000 0x4000000>;
103 reg = <0x79b0000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/compressed/
H A Dmisc.c16 * which should point to addresses in RAM and cleared to 0 on start.
37 int status, i = 0x4000000; in icedcc_putc()
40 if (--i < 0) in icedcc_putc()
43 asm volatile ("mrc p14, 0, %0, c0, c1, 0" : "=r" (status)); in icedcc_putc()
46 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); in icedcc_putc()
54 int status, i = 0x4000000; in icedcc_putc()
57 if (--i < 0) in icedcc_putc()
60 asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); in icedcc_putc()
63 asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); in icedcc_putc()
70 int status, i = 0x4000000; in icedcc_putc()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3358m-vehicle-v10.dts18 reg = <0x00000000 0x0 0x0 0x20000000>;
31 reg = <0x0 0x00000 0x0 0x200000>;
37 reg = <0x0 0x4000000 0x0 0x4000000>;
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_8_0_sh_mask.h27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/
H A Djz4740.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
H A Djz4725b.dtsi12 #size-cells = <0>;
14 cpu0: cpu@0 {
16 compatible = "ingenic,xburst-mxu1.0";
17 reg = <0>;
25 #address-cells = <0>;
33 reg = <0x10001000 0x14>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
55 reg = <0x10000000 0x100>;
65 reg = <0x10002000 0x1000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dti_qspi.txt23 parameters for Mode-0 and Mode-3 operations, which needs to be set up by
24 the bootloader (U-Boot). Default configuration only supports Mode-0
34 reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
37 #size-cells = <0>;
45 reg = <0x4b300000 0x100>,
46 <0x5c000000 0x4000000>,
48 syscon-chipselects = <&scm_conf 0x558>;
50 #size-cells = <0>;
/OK3568_Linux_fs/u-boot/include/environment/ti/
H A Ddfu.h14 "boot part 0 1;" \
15 "rootfs part 0 2;" \
16 "MLO fat 0 1;" \
17 "MLO.raw raw 0x100 0x100;" \
18 "u-boot.img.raw raw 0x300 0x1000;" \
19 "u-env.raw raw 0x1300 0x200;" \
20 "spl-os-args.raw raw 0x1500 0x200;" \
21 "spl-os-image.raw raw 0x1700 0x6900;" \
22 "spl-os-args fat 0 1;" \
23 "spl-os-image fat 0 1;" \
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
34 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
35 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
36 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (D6) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
37 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (D7) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
38 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (B7) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
39 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D8) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/bsc9132qds/
H A Dtlb.c11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13 MAS3_SX|MAS3_SW|MAS3_SR, 0,
14 0, 0, BOOKE_PAGESZ_4K, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dcpu.h32 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
33 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
34 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
35 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
36 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
37 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
38 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
39 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
40 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
41 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt25 first address cell and it may accept values 0..N-1
76 it can be in range [0-3]. For compatible
105 Minimum value is 1 (0 treated as 1).
110 Minimum value is 1 (0 treated as 1).
117 Minimum value is 1 (0 treated as 1).
122 Minimum value is 1 (0 treated as 1).
127 Minimum value is 1 (0 treated as 1).
134 Minimum value is 1 (0 treated as 1).
145 clocks = <&clkaemif 0>;
148 reg = <0x21000A00 0x00000100>;
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dtopic_miami.h22 #define CONFIG_ENV_SIZE 0x8000
24 #define CONFIG_ENV_OFFSET 0x80000
29 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
50 #define CONFIG_SYS_MEMTEST_START 0
52 #define CONFIG_SYS_MEMTEST_END 0x18000000
66 "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \
69 "if load usb 0 0x1900000 ${bootscript}; then "\
70 "source 0x1900000; fi; " \
71 "load usb 0 ${kernel_addr} ${kernel_image} && " \
72 "load usb 0 ${devicetree_addr} ${devicetree_image} && " \
[all …]
H A Dpb1x00.h37 "panic=1\0" \
38 "bootfile=/vmlinux.img\0" \
39 "load=tftp 80500000 ${u-boot}\0" \
55 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
57 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
59 #define CONFIG_SYS_MEMTEST_START 0x80100000
61 #define CONFIG_SYS_MEMTEST_START 0x80200000
62 #define CONFIG_SYS_MEMTEST_END 0x83800000
70 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
71 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
[all …]
/OK3568_Linux_fs/u-boot/board/sbc8548/
H A Dtlb.c14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/atheros/atlx/
H A Datlx.h23 #define SPEED_0 0xffff
30 #define MEDIA_TYPE_AUTO_SENSOR 0
33 #define REG_PM_CTRLSTAT 0x44
35 #define REG_PCIE_CAP_LIST 0x58
37 #define REG_VPD_CAP 0x6C
38 #define VPD_CAP_ID_MASK 0xFF
39 #define VPD_CAP_ID_SHIFT 0
40 #define VPD_CAP_NEXT_PTR_MASK 0xFF
42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
44 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/configs/
H A Dtrizeps4_defconfig77 CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
82 CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
/OK3568_Linux_fs/kernel/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]

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