1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3358m-vehicle-ddr3.dtsi" 10*4882a593Smuzhiyun#include "rk3358-linux.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip linux RK3358M VEHICLE DDR3 board"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3358m-vehicle-ddr3-v10-linux", "rockchip,px30", "rockchip,rk3358"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun memory: memory { 17*4882a593Smuzhiyun device_type = "memory"; 18*4882a593Smuzhiyun reg = <0x00000000 0x0 0x0 0x20000000>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun ramdisk: ramdisk { 22*4882a593Smuzhiyun compatible = "rockchip,ramdisk"; 23*4882a593Smuzhiyun memory-region = <&ramdisk_r>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun reserved-memory { 27*4882a593Smuzhiyun #address-cells = <2>; 28*4882a593Smuzhiyun #size-cells = <2>; 29*4882a593Smuzhiyun ranges; 30*4882a593Smuzhiyun atf: atf@40000 { 31*4882a593Smuzhiyun reg = <0x0 0x00000 0x0 0x200000>; 32*4882a593Smuzhiyun no-map; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun ramdisk_r: ramdisk_r@4000000 { 36*4882a593Smuzhiyun // Do not exceed 132MB which used by TEE 37*4882a593Smuzhiyun reg = <0x0 0x4000000 0x0 0x4000000>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun}; 41