Lines Matching +full:0 +full:x4000000

11 	/* TLB 0 - for temp stack in cache */
12 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
13 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
14 			0, 0, BOOKE_PAGESZ_4K, 0),
15 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
17 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 			0, 0, BOOKE_PAGESZ_4K, 0),
19 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
21 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 			0, 0, BOOKE_PAGESZ_4K, 0),
23 	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
25 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 			0, 0, BOOKE_PAGESZ_4K, 0),
30 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
32 		      0, 0, BOOKE_PAGESZ_4K, 1),
34 	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
36 		      0, 10, BOOKE_PAGESZ_4K, 1),
42 			0, 1, BOOKE_PAGESZ_1M, 1),
47 		      MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
52 			0, 3, BOOKE_PAGESZ_64M, 1),
54 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
55 			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
57 			0, 4, BOOKE_PAGESZ_64M, 1),
63 			0, 6, BOOKE_PAGESZ_256M, 1),
68 			0, 7, BOOKE_PAGESZ_64K, 1),
74 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
75 		      0, 8, BOOKE_PAGESZ_1G, 1),
82 			0, 9, BOOKE_PAGESZ_256K, 1),
88 			0, 5, BOOKE_PAGESZ_1M, 1),