1*4882a593SmuzhiyunTI QSPI controller. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi". 5*4882a593Smuzhiyun- reg: Should contain QSPI registers location and length. 6*4882a593Smuzhiyun- reg-names: Should contain the resource reg names. 7*4882a593Smuzhiyun - qspi_base: Qspi configuration register Address space 8*4882a593Smuzhiyun - qspi_mmap: Memory mapped Address space 9*4882a593Smuzhiyun - (optional) qspi_ctrlmod: Control module Address space 10*4882a593Smuzhiyun- interrupts: should contain the qspi interrupt number. 11*4882a593Smuzhiyun- #address-cells, #size-cells : Must be present if the device has sub-nodes 12*4882a593Smuzhiyun- ti,hwmods: Name of the hwmod associated to the QSPI 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRecommended properties: 15*4882a593Smuzhiyun- spi-max-frequency: Definition as per 16*4882a593Smuzhiyun Documentation/devicetree/bindings/spi/spi-bus.txt 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- syscon-chipselects: Handle to system control region contains QSPI 20*4882a593Smuzhiyun chipselect register and offset of that register. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunNOTE: TI QSPI controller requires different pinmux and IODelay 23*4882a593Smuzhiyunparameters for Mode-0 and Mode-3 operations, which needs to be set up by 24*4882a593Smuzhiyunthe bootloader (U-Boot). Default configuration only supports Mode-0 25*4882a593Smuzhiyunoperation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be 26*4882a593Smuzhiyunspecified in the slave nodes of TI QSPI controller without appropriate 27*4882a593Smuzhiyunmodification to bootloader. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunFor am4372: 32*4882a593Smuzhiyunqspi: qspi@47900000 { 33*4882a593Smuzhiyun compatible = "ti,am4372-qspi"; 34*4882a593Smuzhiyun reg = <0x47900000 0x100>, <0x30000000 0x4000000>; 35*4882a593Smuzhiyun reg-names = "qspi_base", "qspi_mmap"; 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <0>; 38*4882a593Smuzhiyun spi-max-frequency = <25000000>; 39*4882a593Smuzhiyun ti,hwmods = "qspi"; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunFor dra7xx: 43*4882a593Smuzhiyunqspi: qspi@4b300000 { 44*4882a593Smuzhiyun compatible = "ti,dra7xxx-qspi"; 45*4882a593Smuzhiyun reg = <0x4b300000 0x100>, 46*4882a593Smuzhiyun <0x5c000000 0x4000000>, 47*4882a593Smuzhiyun reg-names = "qspi_base", "qspi_mmap"; 48*4882a593Smuzhiyun syscon-chipselects = <&scm_conf 0x558>; 49*4882a593Smuzhiyun #address-cells = <1>; 50*4882a593Smuzhiyun #size-cells = <0>; 51*4882a593Smuzhiyun spi-max-frequency = <48000000>; 52*4882a593Smuzhiyun ti,hwmods = "qspi"; 53*4882a593Smuzhiyun}; 54