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/OK3568_Linux_fs/kernel/drivers/misc/habanalabs/include/goya/asic_reg/
H A Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk.h29 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
30 #define BOOST_CLK_CON 0x0008
31 #define BOOST_BOOST_CON 0x000c
32 #define BOOST_SWITCH_CNT 0x0010
33 #define BOOST_HIGH_PERF_CNT0 0x0014
34 #define BOOST_HIGH_PERF_CNT1 0x0018
35 #define BOOST_STATIS_THRESHOLD 0x001c
36 #define BOOST_SHORT_SWITCH_CNT 0x0020
37 #define BOOST_SWITCH_THRESHOLD 0x0024
38 #define BOOST_FSM_STATUS 0x0028
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-rockchip/
H A Drv1106_pm.h9 #define RV1106_WAKEUP_TO_SYSTEM_RESET 0
11 #define RV1106_PERIGRF_OFFSET 0x0
12 #define RV1106_VENCGRF_OFFSET 0x10000
13 #define RV1106_NPUGRF_OFFSET 0x18000
14 #define RV1106_PMUGRF_OFFSET 0x20000
15 #define RV1106_DDRGRF_OFFSET 0x30000
16 #define RV1106_COREGRF_OFFSET 0x40000
17 #define RV1106_VIGRF_OFFSET 0x50000
18 #define RV1106_VOGRF_OFFSET 0x60000
20 #define RV1106_PERISGRF_OFFSET 0x70000
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbtc8822bwifionly.c9 halwifionly_phy_set_bb_reg(wifionlycfg, 0x4c, 0x01800000, 0x2); in ex_hal8822b_wifi_only_hw_config()
11 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcb4, 0xff, 0x77); in ex_hal8822b_wifi_only_hw_config()
13 halwifionly_phy_set_bb_reg(wifionlycfg, 0x974, 0x300, 0x3); in ex_hal8822b_wifi_only_hw_config()
15 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1990, 0x300, 0x0); in ex_hal8822b_wifi_only_hw_config()
17 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x80000, 0x0); in ex_hal8822b_wifi_only_hw_config()
19 halwifionly_phy_set_bb_reg(wifionlycfg, 0x70, 0xff000000, 0x0e); in ex_hal8822b_wifi_only_hw_config()
20 /*gnt_wl=1 , gnt_bt=0*/ in ex_hal8822b_wifi_only_hw_config()
21 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1704, 0xffffffff, 0x7700); in ex_hal8822b_wifi_only_hw_config()
22 halwifionly_phy_set_bb_reg(wifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); in ex_hal8822b_wifi_only_hw_config()
41 halwifionly_phy_set_bb_reg(wifionlycfg, 0xcbc, 0x300, 0x1); in hal8822b_wifi_only_switch_antenna()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723bs/hal/btc/
H A Dhalbtc8822bwifionly.c25 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); in ex_hal8822b_wifi_only_hw_config()
27 halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77); in ex_hal8822b_wifi_only_hw_config()
29 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3); in ex_hal8822b_wifi_only_hw_config()
31 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0); in ex_hal8822b_wifi_only_hw_config()
33 halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0); in ex_hal8822b_wifi_only_hw_config()
35 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e); in ex_hal8822b_wifi_only_hw_config()
36 /*gnt_wl=1 , gnt_bt=0*/ in ex_hal8822b_wifi_only_hw_config()
37 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700); in ex_hal8822b_wifi_only_hw_config()
38 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); in ex_hal8822b_wifi_only_hw_config()
66 halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x300, 0x1); in hal8822b_wifi_only_switch_antenna()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/hal/btc/
H A Dhalbtc8822bwifionly.c24 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); in ex_hal8822b_wifi_only_hw_config()
26 halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0xff, 0x77); in ex_hal8822b_wifi_only_hw_config()
28 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x974, 0x300, 0x3); in ex_hal8822b_wifi_only_hw_config()
30 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1990, 0x300, 0x0); in ex_hal8822b_wifi_only_hw_config()
32 halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x80000, 0x0); in ex_hal8822b_wifi_only_hw_config()
34 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0xff000000, 0x0e); in ex_hal8822b_wifi_only_hw_config()
35 /*gnt_wl=1 , gnt_bt=0*/ in ex_hal8822b_wifi_only_hw_config()
36 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700); in ex_hal8822b_wifi_only_hw_config()
37 halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); in ex_hal8822b_wifi_only_hw_config()
75 halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcbc, 0x300, 0x1); in hal8822b_wifi_only_switch_antenna()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Ddib0090.c25 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
31 } while (0)
40 #define EN_LNA0 0x8000
41 #define EN_LNA1 0x4000
42 #define EN_LNA2 0x2000
43 #define EN_LNA3 0x1000
44 #define EN_MIX0 0x0800
45 #define EN_MIX1 0x0400
46 #define EN_MIX2 0x0200
47 #define EN_MIX3 0x0100
[all …]
/OK3568_Linux_fs/buildroot/dl/unixbench/git/UnixBench/pgms/
H A Dgfx-x11180 'trap300' => [ 11600.0, "Fill 300x300 trapezoid" ],
184 'strap300' => [ 11700.0, "Fill 300x300 stippled trapezoid (8x8 stipple)" ],
188 'ostrap300' => [ 11600.0, "Fill 300x300 opaque stippled trapezoid (8x8 stipple)" ],
192 'tiletrap300' => [ 11600.0, "Fill 300x300 tiled trapezoid (4x4 tile)" ],
196 'oddstrap300' => [ 2090.0, "Fill 300x300 stippled trapezoid (17x15 stipple)" ],
200 'oddostrap300' => [ 2080.0, "Fill 300x300 opaque stippled trapezoid (17x15 stipple)" ],
204 'oddtiletrap300' => [ 2080.0, "Fill 300x300 tiled trapezoid (17x15 tile)" ],
208 'bigstrap300' => [ 1260.0, "Fill 300x300 stippled trapezoid (161x145 stipple)" ],
212 'bigostrap300' => [ 1420.0, "Fill 300x300 opaque stippled trapezoid (161x145 stipple)" ],
216 'bigtiletrap300' => [ 2350.0, "Fill 300x300 tiled trapezoid (161x145 tile)" ],
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/bt8xx/
H A Dbttv-audio-hook.c30 for (loops = 17; loops >= 0 ; loops--) { in winview_volume()
70 gpio_inout(0x300, 0x300); in gvbctv3pci_audio()
74 con = 0x000; in gvbctv3pci_audio()
77 con = 0x300; in gvbctv3pci_audio()
80 con = 0x200; in gvbctv3pci_audio()
83 gpio_bits(0x300, con); in gvbctv3pci_audio()
97 con = 0x300; in gvbctv5pci_audio()
100 con = 0x100; in gvbctv5pci_audio()
103 con = 0x000; in gvbctv5pci_audio()
106 if (con != (val & 0x300)) { in gvbctv5pci_audio()
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/tegra/fuse/
H A Dfuse-tegra30.c21 #define FUSE_BEGIN 0x100
24 #define FUSE_VENDOR_CODE 0x100
25 #define FUSE_FAB_CODE 0x104
26 #define FUSE_LOT_CODE_0 0x108
27 #define FUSE_LOT_CODE_1 0x10c
28 #define FUSE_WAFER_ID 0x110
29 #define FUSE_X_COORDINATE 0x114
30 #define FUSE_Y_COORDINATE 0x118
32 #define FUSE_HAS_REVISION_INFO BIT(0)
45 return 0; in tegra30_fuse_read_early()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-orion5x/
H A Dbridge-regs.h14 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
16 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
18 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
19 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
21 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
23 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
25 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
27 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
29 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
31 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3588.h68 unsigned int reserved0[16];/* Address Offset: 0x0240 */
69 unsigned int mode_con00;/* Address Offset: 0x0280 */
70 unsigned int reserved1[31];/* Address Offset: 0x0284 */
71 unsigned int clksel_con[178]; /* Address Offset: 0x0300 */
72 unsigned int reserved2[142];/* Address Offset: 0x05c8 */
73 unsigned int clkgate_con[78];/* Address Offset: 0x0800 */
74 unsigned int reserved3[50];/* Address Offset: 0x0938 */
75 unsigned int softrst_con[78];/* Address Offset: 0x0400 */
76 unsigned int reserved4[50];/* Address Offset: 0x0b38 */
77 unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h11 #define RF_DATA 0x1d4
13 #define rPMAC_Reset 0x100
14 #define rPMAC_TxStart 0x104
15 #define rPMAC_TxLegacySIG 0x108
16 #define rPMAC_TxHTSIG1 0x10c
17 #define rPMAC_TxHTSIG2 0x110
18 #define rPMAC_PHYDebug 0x114
19 #define rPMAC_TxPacketNum 0x118
20 #define rPMAC_TxIdle 0x11c
21 #define rPMAC_TxMACHeader0 0x120
[all …]
/OK3568_Linux_fs/kernel/arch/sh/drivers/pci/
H A Dfixups-snapgear.c26 case 11: irq = evt2irq(0x300); break; /* USB */ in pcibios_map_platform_irq()
27 case 12: irq = evt2irq(0x360); break; /* PCMCIA */ in pcibios_map_platform_irq()
28 case 13: irq = evt2irq(0x2a0); break; /* eth0 */ in pcibios_map_platform_irq()
29 case 14: irq = evt2irq(0x300); break; /* eth1 */ in pcibios_map_platform_irq()
30 case 15: irq = evt2irq(0x360); break; /* safenet (unused) */ in pcibios_map_platform_irq()
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx7ulp-evk.dts18 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
22 bcmdhd_wlan_0: bcmdhd_wlan@0 {
31 reg = <0x60000000 0x40000000>;
37 pinctrl-0 = <&pinctrl_backlight>;
47 #reset-cells = <0>;
53 #size-cells = <0>;
65 reg_usb_otg1_vbus: regulator@0 {
67 reg = <0>;
69 pinctrl-0 = <&pinctrl_usb_otg1>;
73 gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
[all …]
H A Dat91sam9x5_can.dtsi19 #clock-cells = <0>;
24 #clock-cells = <0>;
32 reg = <0xf8000000 0x300>;
35 pinctrl-0 = <&pinctrl_can0_rx_tx>;
43 reg = <0xf8004000 0x300>;
46 pinctrl-0 = <&pinctrl_can1_rx_tx>;
H A Dsama5d3_can.dtsi38 #clock-cells = <0>;
40 atmel,clk-output-range = <0 66000000>;
44 #clock-cells = <0>;
46 atmel,clk-output-range = <0 66000000>;
53 reg = <0xf000c000 0x300>;
56 pinctrl-0 = <&pinctrl_can0_rx_tx>;
64 reg = <0xf8010000 0x300>;
67 pinctrl-0 = <&pinctrl_can1_rx_tx>;
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dat91sam9x5_can.dtsi17 reg = <0xf8000000 0x300>;
20 pinctrl-0 = <&pinctrl_can0_rx_tx>;
28 reg = <0xf8004000 0x300>;
31 pinctrl-0 = <&pinctrl_can1_rx_tx>;
H A Dsama5d3_can.dtsi36 reg = <0xf000c000 0x300>;
39 pinctrl-0 = <&pinctrl_can0_rx_tx>;
47 reg = <0xf8010000 0x300>;
50 pinctrl-0 = <&pinctrl_can1_rx_tx>;
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml129 enum: [0, 1]
150 enum: [0, 2]
151 default: 0
172 reg = <0xe0100000 0x1000>;
176 interrupts = <0 24 4>;
182 reg = <0xe2800000 0x1000>;
186 interrupts = <0 24 4>;
197 reg = <0xfe330000 0x10000>;
207 #clock-cells = <0>;
214 interrupts = <0 48 4>;
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]

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