1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with 3*4882a593Smuzhiyun * CAN support 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Licensed under GPLv2. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun ahb { 15*4882a593Smuzhiyun apb { 16*4882a593Smuzhiyun pinctrl@fffff200 { 17*4882a593Smuzhiyun can0 { 18*4882a593Smuzhiyun pinctrl_can0_rx_tx: can0_rx_tx { 19*4882a593Smuzhiyun atmel,pins = 20*4882a593Smuzhiyun <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ 21*4882a593Smuzhiyun AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun can1 { 26*4882a593Smuzhiyun pinctrl_can1_rx_tx: can1_rx_tx { 27*4882a593Smuzhiyun atmel,pins = 28*4882a593Smuzhiyun <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */ 29*4882a593Smuzhiyun AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */ 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun pmc: pmc@fffffc00 { 36*4882a593Smuzhiyun periphck { 37*4882a593Smuzhiyun can0_clk: can0_clk@40 { 38*4882a593Smuzhiyun #clock-cells = <0>; 39*4882a593Smuzhiyun reg = <40>; 40*4882a593Smuzhiyun atmel,clk-output-range = <0 66000000>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun can1_clk: can1_clk@41 { 44*4882a593Smuzhiyun #clock-cells = <0>; 45*4882a593Smuzhiyun reg = <41>; 46*4882a593Smuzhiyun atmel,clk-output-range = <0 66000000>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun can0: can@f000c000 { 52*4882a593Smuzhiyun compatible = "atmel,at91sam9x5-can"; 53*4882a593Smuzhiyun reg = <0xf000c000 0x300>; 54*4882a593Smuzhiyun interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; 55*4882a593Smuzhiyun pinctrl-names = "default"; 56*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can0_rx_tx>; 57*4882a593Smuzhiyun clocks = <&can0_clk>; 58*4882a593Smuzhiyun clock-names = "can_clk"; 59*4882a593Smuzhiyun status = "disabled"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun can1: can@f8010000 { 63*4882a593Smuzhiyun compatible = "atmel,at91sam9x5-can"; 64*4882a593Smuzhiyun reg = <0xf8010000 0x300>; 65*4882a593Smuzhiyun interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; 66*4882a593Smuzhiyun pinctrl-names = "default"; 67*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_can1_rx_tx>; 68*4882a593Smuzhiyun clocks = <&can1_clk>; 69*4882a593Smuzhiyun clock-names = "can_clk"; 70*4882a593Smuzhiyun status = "disabled"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun}; 75