1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Orion CPU Bridge Registers 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 5*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 6*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_ARCH_BRIDGE_REGS_H 10*4882a593Smuzhiyun #define __ASM_ARCH_BRIDGE_REGS_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "orion5x.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108) 19*4882a593Smuzhiyun #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define BRIDGE_INT_TIMER1_CLR (~0x0004) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300) 34*4882a593Smuzhiyun #define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300) 35*4882a593Smuzhiyun #endif 36