Lines Matching +full:0 +full:x300
18 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
22 bcmdhd_wlan_0: bcmdhd_wlan@0 {
31 reg = <0x60000000 0x40000000>;
37 pinctrl-0 = <&pinctrl_backlight>;
47 #reset-cells = <0>;
53 #size-cells = <0>;
65 reg_usb_otg1_vbus: regulator@0 {
67 reg = <0>;
69 pinctrl-0 = <&pinctrl_usb_otg1>;
73 gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
83 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
102 pinctrl-0 = <&pinctrl_extcon_usb1>;
164 pinctrl-0 = <&pinctrl_hog_1>;
169 ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */
170 ULP1_PAD_PTC1__PTC1 0x20100
171 ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */
172 ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */
173 ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */
174 ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */
180 ULP1_PAD_PTF2__PTF2 0x20100
186 ULP1_PAD_PTC4__LPI2C5_SCL 0x527
187 ULP1_PAD_PTC5__LPI2C5_SDA 0x527
193 ULP1_PAD_PTC19__PTC19 0x20103
199 ULP1_PAD_PTC3__LPUART4_RX 0x400
200 ULP1_PAD_PTC2__LPUART4_TX 0x400
206 ULP1_PAD_PTE10__LPUART6_TX 0x400
207 ULP1_PAD_PTE11__LPUART6_RX 0x400
208 ULP1_PAD_PTE9__LPUART6_RTS_B 0x400
209 ULP1_PAD_PTE8__LPUART6_CTS_B 0x400
210 ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */
216 ULP1_PAD_PTF14__LPUART7_TX 0x400
217 ULP1_PAD_PTF15__LPUART7_RX 0x400
218 ULP1_PAD_PTF13__LPUART7_RTS_B 0x400
219 ULP1_PAD_PTF12__LPUART7_CTS_B 0x400
225 ULP1_PAD_PTD1__SDHC0_CMD 0x843
226 ULP1_PAD_PTD2__SDHC0_CLK 0x10843
227 ULP1_PAD_PTD7__SDHC0_D3 0x843
228 ULP1_PAD_PTD8__SDHC0_D2 0x843
229 ULP1_PAD_PTD9__SDHC0_D1 0x843
230 ULP1_PAD_PTD10__SDHC0_D0 0x843
236 ULP1_PAD_PTD1__SDHC0_CMD 0x843
237 ULP1_PAD_PTD2__SDHC0_CLK 0x843
238 ULP1_PAD_PTD3__SDHC0_D7 0x843
239 ULP1_PAD_PTD4__SDHC0_D6 0x843
240 ULP1_PAD_PTD5__SDHC0_D5 0x843
241 ULP1_PAD_PTD6__SDHC0_D4 0x843
242 ULP1_PAD_PTD7__SDHC0_D3 0x843
243 ULP1_PAD_PTD8__SDHC0_D2 0x843
244 ULP1_PAD_PTD9__SDHC0_D1 0x843
245 ULP1_PAD_PTD10__SDHC0_D0 0x843
251 ULP1_PAD_PTF12__LPI2C7_SCL 0x527
252 ULP1_PAD_PTF13__LPI2C7_SDA 0x527
258 ULP1_PAD_PTF16__LPSPI3_SIN 0x300
259 ULP1_PAD_PTF17__LPSPI3_SOUT 0x300
260 ULP1_PAD_PTF18__LPSPI3_SCK 0x300
261 ULP1_PAD_PTF19__LPSPI3_PCS0 0x300
267 ULP1_PAD_PTC0__PTC0 0x30100
273 ULP1_PAD_PTC8__PTC8 0x30103
279 ULP1_PAD_PTE3__SDHC1_CMD 0x843
280 ULP1_PAD_PTE2__SDHC1_CLK 0x843
281 ULP1_PAD_PTE1__SDHC1_D0 0x843
282 ULP1_PAD_PTE0__SDHC1_D1 0x843
283 ULP1_PAD_PTE5__SDHC1_D2 0x843
284 ULP1_PAD_PTE4__SDHC1_D3 0x843
290 ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */
296 ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */
324 hsync-active = <0>;
325 vsync-active = <0>;
327 pixelclk-active = <0>;
335 #size-cells = <0>;
337 pinctrl-0 = <&pinctrl_lpi2c7>;
342 #size-cells = <0>;
344 pinctrl-0 = <&pinctrl_lpi2c5>;
349 reg = <0x20>;
354 reg = <0x1e>;
359 reg = <0x60>;
365 #size-cells = <0>;
367 pinctrl-0 = <&pinctrl_lpspi3>;
370 spidev0: spi@0 {
371 reg = <0>;
379 pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
387 pinctrl-0 = <&pinctrl_lpuart4>;
393 pinctrl-0 = <&pinctrl_lpuart6>;
399 pinctrl-0 = <&pinctrl_lpuart7>;
409 extcon = <0>, <&extcon_usb1>;
418 pinctrl-0 = <&pinctrl_usdhc0>;