xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/at91sam9x5_can.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
3*4882a593Smuzhiyun * Ethernet interface.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Licensed under GPLv2.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h>
11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	ahb {
15*4882a593Smuzhiyun		apb {
16*4882a593Smuzhiyun			pmc: pmc@fffffc00 {
17*4882a593Smuzhiyun				periphck {
18*4882a593Smuzhiyun					can0_clk: can0_clk@29 {
19*4882a593Smuzhiyun						#clock-cells = <0>;
20*4882a593Smuzhiyun						reg = <29>;
21*4882a593Smuzhiyun					};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun					can1_clk: can1_clk@30 {
24*4882a593Smuzhiyun						#clock-cells = <0>;
25*4882a593Smuzhiyun						reg = <30>;
26*4882a593Smuzhiyun					};
27*4882a593Smuzhiyun				};
28*4882a593Smuzhiyun			};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun			can0: can@f8000000 {
31*4882a593Smuzhiyun				compatible = "atmel,at91sam9x5-can";
32*4882a593Smuzhiyun				reg = <0xf8000000 0x300>;
33*4882a593Smuzhiyun				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
34*4882a593Smuzhiyun				pinctrl-names = "default";
35*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_can0_rx_tx>;
36*4882a593Smuzhiyun				clocks = <&can0_clk>;
37*4882a593Smuzhiyun				clock-names = "can_clk";
38*4882a593Smuzhiyun				status = "disabled";
39*4882a593Smuzhiyun			};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun			can1: can@f8004000 {
42*4882a593Smuzhiyun				compatible = "atmel,at91sam9x5-can";
43*4882a593Smuzhiyun				reg = <0xf8004000 0x300>;
44*4882a593Smuzhiyun				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
45*4882a593Smuzhiyun				pinctrl-names = "default";
46*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_can1_rx_tx>;
47*4882a593Smuzhiyun				clocks = <&can1_clk>;
48*4882a593Smuzhiyun				clock-names = "can_clk";
49*4882a593Smuzhiyun				status = "disabled";
50*4882a593Smuzhiyun			};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun			pinctrl@fffff400 {
53*4882a593Smuzhiyun				can0 {
54*4882a593Smuzhiyun					pinctrl_can0_rx_tx: can0_rx_tx {
55*4882a593Smuzhiyun						atmel,pins =
56*4882a593Smuzhiyun							<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX0, conflicts with DRXD */
57*4882a593Smuzhiyun							AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* CANTX0, conflicts with DTXD */
58*4882a593Smuzhiyun					};
59*4882a593Smuzhiyun				};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun				can1 {
62*4882a593Smuzhiyun					pinctrl_can1_rx_tx: can1_rx_tx {
63*4882a593Smuzhiyun						atmel,pins =
64*4882a593Smuzhiyun							<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* CANRX1, conflicts with RXD1 */
65*4882a593Smuzhiyun							AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* CANTX1, conflicts with TXD1 */
66*4882a593Smuzhiyun					};
67*4882a593Smuzhiyun				};
68*4882a593Smuzhiyun			};
69*4882a593Smuzhiyun		};
70*4882a593Smuzhiyun	};
71*4882a593Smuzhiyun};
72