Home
last modified time | relevance | path

Searched +full:0 +full:x19c (Results 1 – 25 of 209) sorted by relevance

123456789

/OK3568_Linux_fs/kernel/drivers/media/platform/coda/
H A Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu-sun50i-a100-r.c24 { .index = 3, .shift = 0, .width = 5 },
39 .reg = 0x000,
44 0),
48 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
51 .div = _SUNXI_CCU_DIV(0, 2),
54 .reg = 0x00c,
58 0),
74 .reg = 0x010,
79 0),
92 0x11c, BIT(0), 0);
[all …]
H A Dccu-sun50i-h6-r.c28 { .index = 3, .shift = 0, .width = 5 },
43 .reg = 0x000,
48 0),
52 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
54 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
68 .reg = 0x010,
73 0),
85 0x11c, BIT(0), 0);
87 0x12c, BIT(0), 0);
89 0x13c, BIT(0), 0);
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-cache.json4 "Counter": "0,1,2,3",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
27 "UMask": "0x1",
32 "Counter": "0,1",
33 "EventCode": "0x35",
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/qualcomm/
H A Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/
H A Dfuse.h13 u32 reserved0[64]; /* 0x00 - 0xFC: */
14 u32 production_mode; /* 0x100: FUSE_PRODUCTION_MODE */
15 u32 reserved1[3]; /* 0x104 - 0x10c: */
16 u32 sku_info; /* 0x110 */
17 u32 reserved2[13]; /* 0x114 - 0x144: */
18 u32 fa; /* 0x148: FUSE_FA */
19 u32 reserved3[21]; /* 0x14C - 0x19C: */
20 u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */
/OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-cache.json4 "Counter": "0,1,2,3",
11 "Counter": "0,1",
12 "EventCode": "0x34",
14 "Filter": "filter_state=0x1",
17 "UMask": "0x11",
22 "Counter": "0,1",
23 "EventCode": "0x37",
27 "UMask": "0x1",
32 "Counter": "0,1",
33 "EventCode": "0x35",
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dsama5_matrix.h14 u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
15 u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
16 u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
17 u32 res1[20]; /* 0x100 ~ 0x14c */
18 u32 meier; /* 0x150: Master Error Interrupt Enable Register */
19 u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
20 u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
21 u32 mesr; /* 0x15c: Master Error Status Register */
22 u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
23 u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
[all …]
/OK3568_Linux_fs/kernel/drivers/crypto/qat/qat_common/
H A Dadf_hw_arbiter.c8 #define ADF_ARB_REG_SIZE 0x4
9 #define ADF_ARB_WTR_SIZE 0x20
10 #define ADF_ARB_OFFSET 0x30000
11 #define ADF_ARB_REG_SLOT 0x1000
12 #define ADF_ARB_WTR_OFFSET 0x010
13 #define ADF_ARB_RO_EN_OFFSET 0x090
14 #define ADF_ARB_WQCFG_OFFSET 0x100
15 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
16 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
38 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Daxg.h19 #define HHI_MIPI_CNTL0 0x00
20 #define HHI_GP0_PLL_CNTL 0x40
21 #define HHI_GP0_PLL_CNTL2 0x44
22 #define HHI_GP0_PLL_CNTL3 0x48
23 #define HHI_GP0_PLL_CNTL4 0x4c
24 #define HHI_GP0_PLL_CNTL5 0x50
25 #define HHI_GP0_PLL_STS 0x54
26 #define HHI_GP0_PLL_CNTL1 0x58
27 #define HHI_HIFI_PLL_CNTL 0x80
28 #define HHI_HIFI_PLL_CNTL2 0x84
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dgp_padctrl.h15 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
16 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
17 u32 reserved0[22]; /* 0x08 - 0x5C: */
18 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
19 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
20 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
21 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
22 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
23 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
24 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra114/
H A Dgp_padctrl.h14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dgp_padctrl.h15 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
16 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
17 u32 reserved0[22]; /* 0x08 - 0x5C: */
18 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
19 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
20 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
21 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
22 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
23 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
24 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop.yaml109 reg = <0xff930000 0x19c>,
110 <0xff931000 0x1000>;
124 #size-cells = <0>;
125 vopb_out_edp: endpoint@0 {
126 reg = <0>;
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-armada100/
H A Dmfp.h24 #define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
25 #define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
26 #define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
27 #define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
28 #define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
29 #define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
30 #define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
31 #define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
32 #define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
33 #define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
[all …]
/OK3568_Linux_fs/kernel/tools/perf/arch/powerpc/util/
H A Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Dfsl_mcdmafec.h17 u32 rsvd0; /* 0x000 */
18 u32 eir; /* 0x004 */
19 u32 eimr; /* 0x008 */
20 u32 rsvd1[6]; /* 0x00C - 0x023 */
21 u32 ecr; /* 0x024 */
22 u32 rsvd2[6]; /* 0x028 - 0x03F */
23 u32 mmfr; /* 0x040 */
24 u32 mscr; /* 0x044 */
25 u32 rsvd3[7]; /* 0x048 - 0x063 */
26 u32 mibc; /* 0x064 */
[all …]

123456789