1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 AmLogic, Inc. 4*4882a593Smuzhiyun * Author: Michael Turquette <mturquette@baylibre.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (c) 2017 Amlogic, inc. 7*4882a593Smuzhiyun * Author: Qiufang Dai <qiufang.dai@amlogic.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __AXG_H 11*4882a593Smuzhiyun #define __AXG_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * Clock controller register offsets 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * Register offsets from the data sheet must be multiplied by 4 before 17*4882a593Smuzhiyun * adding them to the base address to get the right value. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define HHI_MIPI_CNTL0 0x00 20*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL 0x40 21*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL2 0x44 22*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL3 0x48 23*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL4 0x4c 24*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL5 0x50 25*4882a593Smuzhiyun #define HHI_GP0_PLL_STS 0x54 26*4882a593Smuzhiyun #define HHI_GP0_PLL_CNTL1 0x58 27*4882a593Smuzhiyun #define HHI_HIFI_PLL_CNTL 0x80 28*4882a593Smuzhiyun #define HHI_HIFI_PLL_CNTL2 0x84 29*4882a593Smuzhiyun #define HHI_HIFI_PLL_CNTL3 0x88 30*4882a593Smuzhiyun #define HHI_HIFI_PLL_CNTL4 0x8C 31*4882a593Smuzhiyun #define HHI_HIFI_PLL_CNTL5 0x90 32*4882a593Smuzhiyun #define HHI_HIFI_PLL_STS 0x94 33*4882a593Smuzhiyun #define HHI_HIFI_PLL_CNTL1 0x98 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define HHI_XTAL_DIVN_CNTL 0xbc 36*4882a593Smuzhiyun #define HHI_GCLK2_MPEG0 0xc0 37*4882a593Smuzhiyun #define HHI_GCLK2_MPEG1 0xc4 38*4882a593Smuzhiyun #define HHI_GCLK2_MPEG2 0xc8 39*4882a593Smuzhiyun #define HHI_GCLK2_OTHER 0xd0 40*4882a593Smuzhiyun #define HHI_GCLK2_AO 0xd4 41*4882a593Smuzhiyun #define HHI_PCIE_PLL_CNTL 0xd8 42*4882a593Smuzhiyun #define HHI_PCIE_PLL_CNTL1 0xdC 43*4882a593Smuzhiyun #define HHI_PCIE_PLL_CNTL2 0xe0 44*4882a593Smuzhiyun #define HHI_PCIE_PLL_CNTL3 0xe4 45*4882a593Smuzhiyun #define HHI_PCIE_PLL_CNTL4 0xe8 46*4882a593Smuzhiyun #define HHI_PCIE_PLL_CNTL5 0xec 47*4882a593Smuzhiyun #define HHI_PCIE_PLL_CNTL6 0xf0 48*4882a593Smuzhiyun #define HHI_PCIE_PLL_STS 0xf4 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define HHI_MEM_PD_REG0 0x100 51*4882a593Smuzhiyun #define HHI_VPU_MEM_PD_REG0 0x104 52*4882a593Smuzhiyun #define HHI_VIID_CLK_DIV 0x128 53*4882a593Smuzhiyun #define HHI_VIID_CLK_CNTL 0x12c 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define HHI_GCLK_MPEG0 0x140 56*4882a593Smuzhiyun #define HHI_GCLK_MPEG1 0x144 57*4882a593Smuzhiyun #define HHI_GCLK_MPEG2 0x148 58*4882a593Smuzhiyun #define HHI_GCLK_OTHER 0x150 59*4882a593Smuzhiyun #define HHI_GCLK_AO 0x154 60*4882a593Smuzhiyun #define HHI_SYS_CPU_CLK_CNTL1 0x15c 61*4882a593Smuzhiyun #define HHI_SYS_CPU_RESET_CNTL 0x160 62*4882a593Smuzhiyun #define HHI_VID_CLK_DIV 0x164 63*4882a593Smuzhiyun #define HHI_SPICC_HCLK_CNTL 0x168 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define HHI_MPEG_CLK_CNTL 0x174 66*4882a593Smuzhiyun #define HHI_VID_CLK_CNTL 0x17c 67*4882a593Smuzhiyun #define HHI_TS_CLK_CNTL 0x190 68*4882a593Smuzhiyun #define HHI_VID_CLK_CNTL2 0x194 69*4882a593Smuzhiyun #define HHI_SYS_CPU_CLK_CNTL0 0x19c 70*4882a593Smuzhiyun #define HHI_VID_PLL_CLK_DIV 0x1a0 71*4882a593Smuzhiyun #define HHI_VPU_CLK_CNTL 0x1bC 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define HHI_VAPBCLK_CNTL 0x1F4 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define HHI_GEN_CLK_CNTL 0x228 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define HHI_VDIN_MEAS_CLK_CNTL 0x250 78*4882a593Smuzhiyun #define HHI_NAND_CLK_CNTL 0x25C 79*4882a593Smuzhiyun #define HHI_SD_EMMC_CLK_CNTL 0x264 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define HHI_MPLL_CNTL 0x280 82*4882a593Smuzhiyun #define HHI_MPLL_CNTL2 0x284 83*4882a593Smuzhiyun #define HHI_MPLL_CNTL3 0x288 84*4882a593Smuzhiyun #define HHI_MPLL_CNTL4 0x28C 85*4882a593Smuzhiyun #define HHI_MPLL_CNTL5 0x290 86*4882a593Smuzhiyun #define HHI_MPLL_CNTL6 0x294 87*4882a593Smuzhiyun #define HHI_MPLL_CNTL7 0x298 88*4882a593Smuzhiyun #define HHI_MPLL_CNTL8 0x29C 89*4882a593Smuzhiyun #define HHI_MPLL_CNTL9 0x2A0 90*4882a593Smuzhiyun #define HHI_MPLL_CNTL10 0x2A4 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define HHI_MPLL3_CNTL0 0x2E0 93*4882a593Smuzhiyun #define HHI_MPLL3_CNTL1 0x2E4 94*4882a593Smuzhiyun #define HHI_PLL_TOP_MISC 0x2E8 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL1 0x2FC 97*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL 0x300 98*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL2 0x304 99*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL3 0x308 100*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL4 0x30c 101*4882a593Smuzhiyun #define HHI_SYS_PLL_CNTL5 0x310 102*4882a593Smuzhiyun #define HHI_SYS_PLL_STS 0x314 103*4882a593Smuzhiyun #define HHI_DPLL_TOP_I 0x318 104*4882a593Smuzhiyun #define HHI_DPLL_TOP2_I 0x31C 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * CLKID index values 108*4882a593Smuzhiyun * 109*4882a593Smuzhiyun * These indices are entirely contrived and do not map onto the hardware. 110*4882a593Smuzhiyun * It has now been decided to expose everything by default in the DT header: 111*4882a593Smuzhiyun * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want 112*4882a593Smuzhiyun * to expose, such as the internal muxes and dividers of composite clocks, 113*4882a593Smuzhiyun * will remain defined here. 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun #define CLKID_MPEG_SEL 8 116*4882a593Smuzhiyun #define CLKID_MPEG_DIV 9 117*4882a593Smuzhiyun #define CLKID_SD_EMMC_B_CLK0_SEL 61 118*4882a593Smuzhiyun #define CLKID_SD_EMMC_B_CLK0_DIV 62 119*4882a593Smuzhiyun #define CLKID_SD_EMMC_C_CLK0_SEL 63 120*4882a593Smuzhiyun #define CLKID_SD_EMMC_C_CLK0_DIV 64 121*4882a593Smuzhiyun #define CLKID_MPLL0_DIV 65 122*4882a593Smuzhiyun #define CLKID_MPLL1_DIV 66 123*4882a593Smuzhiyun #define CLKID_MPLL2_DIV 67 124*4882a593Smuzhiyun #define CLKID_MPLL3_DIV 68 125*4882a593Smuzhiyun #define CLKID_MPLL_PREDIV 70 126*4882a593Smuzhiyun #define CLKID_FCLK_DIV2_DIV 71 127*4882a593Smuzhiyun #define CLKID_FCLK_DIV3_DIV 72 128*4882a593Smuzhiyun #define CLKID_FCLK_DIV4_DIV 73 129*4882a593Smuzhiyun #define CLKID_FCLK_DIV5_DIV 74 130*4882a593Smuzhiyun #define CLKID_FCLK_DIV7_DIV 75 131*4882a593Smuzhiyun #define CLKID_PCIE_PLL 76 132*4882a593Smuzhiyun #define CLKID_PCIE_MUX 77 133*4882a593Smuzhiyun #define CLKID_PCIE_REF 78 134*4882a593Smuzhiyun #define CLKID_GEN_CLK_SEL 82 135*4882a593Smuzhiyun #define CLKID_GEN_CLK_DIV 83 136*4882a593Smuzhiyun #define CLKID_SYS_PLL_DCO 85 137*4882a593Smuzhiyun #define CLKID_FIXED_PLL_DCO 86 138*4882a593Smuzhiyun #define CLKID_GP0_PLL_DCO 87 139*4882a593Smuzhiyun #define CLKID_HIFI_PLL_DCO 88 140*4882a593Smuzhiyun #define CLKID_PCIE_PLL_DCO 89 141*4882a593Smuzhiyun #define CLKID_PCIE_PLL_OD 90 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define NR_CLKS 91 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* include the CLKIDs that have been made part of the DT binding */ 146*4882a593Smuzhiyun #include <dt-bindings/clock/axg-clkc.h> 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #endif /* __AXG_H */ 149