1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h 3*4882a593Smuzhiyun * (C) Copyright 2007 4*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 5*4882a593Smuzhiyun * 2007-08-21: eric miao <eric.miao@marvell.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2010 8*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 9*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 10*4882a593Smuzhiyun * Contributor: Mahavir Jain <mjain@marvell.com> 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __ARMADA100_MFP_H 16*4882a593Smuzhiyun #define __ARMADA100_MFP_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * offset, pull,pF, drv,dF, edge,eF ,afn,aF 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun /* UART1 */ 24*4882a593Smuzhiyun #define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST) 25*4882a593Smuzhiyun #define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST) 26*4882a593Smuzhiyun #define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST) 27*4882a593Smuzhiyun #define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST) 28*4882a593Smuzhiyun #define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM) 29*4882a593Smuzhiyun #define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) 30*4882a593Smuzhiyun #define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM) 31*4882a593Smuzhiyun #define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM) 32*4882a593Smuzhiyun #define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM) 33*4882a593Smuzhiyun #define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM) 34*4882a593Smuzhiyun #define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM) 35*4882a593Smuzhiyun #define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* UART2 */ 38*4882a593Smuzhiyun #define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM) 39*4882a593Smuzhiyun #define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM) 40*4882a593Smuzhiyun #define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM) 41*4882a593Smuzhiyun #define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* UART3 */ 44*4882a593Smuzhiyun #define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM) 45*4882a593Smuzhiyun #define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* I2c */ 48*4882a593Smuzhiyun #define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM) 49*4882a593Smuzhiyun #define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Fast Ethernet */ 52*4882a593Smuzhiyun #define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM) 53*4882a593Smuzhiyun #define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 54*4882a593Smuzhiyun #define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM) 55*4882a593Smuzhiyun #define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM) 56*4882a593Smuzhiyun #define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM) 57*4882a593Smuzhiyun #define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 58*4882a593Smuzhiyun #define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM) 59*4882a593Smuzhiyun #define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM) 60*4882a593Smuzhiyun #define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM) 61*4882a593Smuzhiyun #define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 62*4882a593Smuzhiyun #define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM) 63*4882a593Smuzhiyun #define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM) 64*4882a593Smuzhiyun #define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM) 65*4882a593Smuzhiyun #define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 66*4882a593Smuzhiyun #define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM) 67*4882a593Smuzhiyun #define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM) 68*4882a593Smuzhiyun #define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* SPI */ 71*4882a593Smuzhiyun #define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM) 72*4882a593Smuzhiyun #define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM) 73*4882a593Smuzhiyun #define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM) 74*4882a593Smuzhiyun #define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* More macros can be defined here... */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define MFP_PIN_MAX 117 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #endif /* __ARMADA100_MFP_H */ 81