1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef fsl_mcdmafec_h 11*4882a593Smuzhiyun #define fsl_mcdmafec_h 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Re-use of the definitions */ 14*4882a593Smuzhiyun #include <asm/fec.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun typedef struct fecdma { 17*4882a593Smuzhiyun u32 rsvd0; /* 0x000 */ 18*4882a593Smuzhiyun u32 eir; /* 0x004 */ 19*4882a593Smuzhiyun u32 eimr; /* 0x008 */ 20*4882a593Smuzhiyun u32 rsvd1[6]; /* 0x00C - 0x023 */ 21*4882a593Smuzhiyun u32 ecr; /* 0x024 */ 22*4882a593Smuzhiyun u32 rsvd2[6]; /* 0x028 - 0x03F */ 23*4882a593Smuzhiyun u32 mmfr; /* 0x040 */ 24*4882a593Smuzhiyun u32 mscr; /* 0x044 */ 25*4882a593Smuzhiyun u32 rsvd3[7]; /* 0x048 - 0x063 */ 26*4882a593Smuzhiyun u32 mibc; /* 0x064 */ 27*4882a593Smuzhiyun u32 rsvd4[7]; /* 0x068 - 0x083 */ 28*4882a593Smuzhiyun u32 rcr; /* 0x084 */ 29*4882a593Smuzhiyun u32 rhr; /* 0x088 */ 30*4882a593Smuzhiyun u32 rsvd5[14]; /* 0x08C - 0x0C3 */ 31*4882a593Smuzhiyun u32 tcr; /* 0x0C4 */ 32*4882a593Smuzhiyun u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */ 33*4882a593Smuzhiyun u32 palr; /* 0x0E4 */ 34*4882a593Smuzhiyun u32 paur; /* 0x0E8 */ 35*4882a593Smuzhiyun u32 opd; /* 0x0EC */ 36*4882a593Smuzhiyun u32 rsvd7[10]; /* 0x0F0 - 0x117 */ 37*4882a593Smuzhiyun u32 iaur; /* 0x118 */ 38*4882a593Smuzhiyun u32 ialr; /* 0x11C */ 39*4882a593Smuzhiyun u32 gaur; /* 0x120 */ 40*4882a593Smuzhiyun u32 galr; /* 0x124 */ 41*4882a593Smuzhiyun u32 rsvd8[7]; /* 0x128 - 0x143 */ 42*4882a593Smuzhiyun u32 tfwr; /* 0x144 */ 43*4882a593Smuzhiyun u32 rsvd9[14]; /* 0x148 - 0x17F */ 44*4882a593Smuzhiyun u32 fmc; /* 0x180 */ 45*4882a593Smuzhiyun u32 rfdr; /* 0x184 */ 46*4882a593Smuzhiyun u32 rfsr; /* 0x188 */ 47*4882a593Smuzhiyun u32 rfcr; /* 0x18C */ 48*4882a593Smuzhiyun u32 rlrfp; /* 0x190 */ 49*4882a593Smuzhiyun u32 rlwfp; /* 0x194 */ 50*4882a593Smuzhiyun u32 rfar; /* 0x198 */ 51*4882a593Smuzhiyun u32 rfrp; /* 0x19C */ 52*4882a593Smuzhiyun u32 rfwp; /* 0x1A0 */ 53*4882a593Smuzhiyun u32 tfdr; /* 0x1A4 */ 54*4882a593Smuzhiyun u32 tfsr; /* 0x1A8 */ 55*4882a593Smuzhiyun u32 tfcr; /* 0x1AC */ 56*4882a593Smuzhiyun u32 tlrfp; /* 0x1B0 */ 57*4882a593Smuzhiyun u32 tlwfp; /* 0x1B4 */ 58*4882a593Smuzhiyun u32 tfar; /* 0x1B8 */ 59*4882a593Smuzhiyun u32 tfrp; /* 0x1BC */ 60*4882a593Smuzhiyun u32 tfwp; /* 0x1C0 */ 61*4882a593Smuzhiyun u32 frst; /* 0x1C4 */ 62*4882a593Smuzhiyun u32 ctcwr; /* 0x1C8 */ 63*4882a593Smuzhiyun } fecdma_t; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct fec_info_dma { 66*4882a593Smuzhiyun int index; 67*4882a593Smuzhiyun u32 iobase; 68*4882a593Smuzhiyun u32 pinmux; 69*4882a593Smuzhiyun u32 miibase; 70*4882a593Smuzhiyun int phy_addr; 71*4882a593Smuzhiyun int dup_spd; 72*4882a593Smuzhiyun char *phy_name; 73*4882a593Smuzhiyun int phyname_init; 74*4882a593Smuzhiyun cbd_t *rxbd; /* Rx BD */ 75*4882a593Smuzhiyun cbd_t *txbd; /* Tx BD */ 76*4882a593Smuzhiyun uint rxIdx; 77*4882a593Smuzhiyun uint txIdx; 78*4882a593Smuzhiyun char *txbuf; 79*4882a593Smuzhiyun int initialized; 80*4882a593Smuzhiyun struct fec_info_dma *next; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun u16 rxTask; /* DMA receive Task Number */ 83*4882a593Smuzhiyun u16 txTask; /* DMA Transmit Task Number */ 84*4882a593Smuzhiyun u16 rxPri; /* DMA Receive Priority */ 85*4882a593Smuzhiyun u16 txPri; /* DMA Transmit Priority */ 86*4882a593Smuzhiyun u16 rxInit; /* DMA Receive Initiator */ 87*4882a593Smuzhiyun u16 txInit; /* DMA Transmit Initiator */ 88*4882a593Smuzhiyun u16 usedTbdIdx; /* next transmit BD to clean */ 89*4882a593Smuzhiyun u16 cleanTbdNum; /* the number of available transmit BDs */ 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Bit definitions and macros for IEVENT */ 93*4882a593Smuzhiyun #define FEC_EIR_TXERR (0x00040000) 94*4882a593Smuzhiyun #define FEC_EIR_RXERR (0x00020000) 95*4882a593Smuzhiyun #undef FEC_EIR_CLEAR_ALL 96*4882a593Smuzhiyun #define FEC_EIR_CLEAR_ALL (0xFFFE0000) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Bit definitions and macros for R_HASH */ 99*4882a593Smuzhiyun #define FEC_RHASH_FCE_DC (0x80000000) 100*4882a593Smuzhiyun #define FEC_RHASH_MULTCAST (0x40000000) 101*4882a593Smuzhiyun #define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Bit definitions and macros for FEC_TFWR */ 104*4882a593Smuzhiyun #undef FEC_TFWR_X_WMRK 105*4882a593Smuzhiyun #undef FEC_TFWR_X_WMRK_64 106*4882a593Smuzhiyun #undef FEC_TFWR_X_WMRK_128 107*4882a593Smuzhiyun #undef FEC_TFWR_X_WMRK_192 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK(x) ((x)&0x0F) 110*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_64 (0x00) 111*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_128 (0x01) 112*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_192 (0x02) 113*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_256 (0x03) 114*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_320 (0x04) 115*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_384 (0x05) 116*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_448 (0x06) 117*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_512 (0x07) 118*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_576 (0x08) 119*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_640 (0x09) 120*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_704 (0x0A) 121*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_768 (0x0B) 122*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_832 (0x0C) 123*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_896 (0x0D) 124*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_960 (0x0E) 125*4882a593Smuzhiyun #define FEC_TFWR_X_WMRK_1024 (0x0F) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* FIFO definitions */ 128*4882a593Smuzhiyun /* Bit definitions and macros for FSTAT */ 129*4882a593Smuzhiyun #define FIFO_STAT_IP (0x80000000) 130*4882a593Smuzhiyun #define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24) 131*4882a593Smuzhiyun #define FIFO_STAT_FAE (0x00800000) 132*4882a593Smuzhiyun #define FIFO_STAT_RXW (0x00400000) 133*4882a593Smuzhiyun #define FIFO_STAT_UF (0x00200000) 134*4882a593Smuzhiyun #define FIFO_STAT_OF (0x00100000) 135*4882a593Smuzhiyun #define FIFO_STAT_FR (0x00080000) 136*4882a593Smuzhiyun #define FIFO_STAT_FULL (0x00040000) 137*4882a593Smuzhiyun #define FIFO_STAT_ALARM (0x00020000) 138*4882a593Smuzhiyun #define FIFO_STAT_EMPTY (0x00010000) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* Bit definitions and macros for FCTRL */ 141*4882a593Smuzhiyun #define FIFO_CTRL_WCTL (0x40000000) 142*4882a593Smuzhiyun #define FIFO_CTRL_WFR (0x20000000) 143*4882a593Smuzhiyun #define FIFO_CTRL_FRAME (0x08000000) 144*4882a593Smuzhiyun #define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24) 145*4882a593Smuzhiyun #define FIFO_CTRL_IPMASK (0x00800000) 146*4882a593Smuzhiyun #define FIFO_CTRL_FAEMASK (0x00400000) 147*4882a593Smuzhiyun #define FIFO_CTRL_RXWMASK (0x00200000) 148*4882a593Smuzhiyun #define FIFO_CTRL_UFMASK (0x00100000) 149*4882a593Smuzhiyun #define FIFO_CTRL_OFMASK (0x00080000) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #endif /* fsl_mcdmafec_h */ 152