xref: /OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/sama5_matrix.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Bus Matrix header file for the SAMA5 family
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2014 Atmel
5*4882a593Smuzhiyun  *		      Bo Shen <voice.shen@atmel.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #ifndef __SAMA5_MATRIX_H
11*4882a593Smuzhiyun #define __SAMA5_MATRIX_H
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun struct atmel_matrix {
14*4882a593Smuzhiyun 	u32 mcfg[16];	/* 0x00 ~ 0x3c: Master Configuration Register */
15*4882a593Smuzhiyun 	u32 scfg[16];	/* 0x40 ~ 0x7c: Slave Configuration Register */
16*4882a593Smuzhiyun 	u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
17*4882a593Smuzhiyun 	u32 res1[20];	/* 0x100 ~ 0x14c */
18*4882a593Smuzhiyun 	u32 meier;	/* 0x150: Master Error Interrupt Enable Register */
19*4882a593Smuzhiyun 	u32 meidr;	/* 0x154: Master Error Interrupt Disable Register */
20*4882a593Smuzhiyun 	u32 meimr;	/* 0x158: Master Error Interrupt Mask Register */
21*4882a593Smuzhiyun 	u32 mesr;	/* 0x15c: Master Error Status Register */
22*4882a593Smuzhiyun 	u32 mear[16];	/* 0x160 ~ 0x19c: Master Error Address Register */
23*4882a593Smuzhiyun 	u32 res2[17];	/* 0x1A0 ~ 0x1E0 */
24*4882a593Smuzhiyun 	u32 wpmr;	/* 0x1E4: Write Protection Mode Register */
25*4882a593Smuzhiyun 	u32 wpsr;	/* 0x1E8: Write Protection Status Register */
26*4882a593Smuzhiyun 	u32 res3[5];	/* 0x1EC ~ 0x1FC */
27*4882a593Smuzhiyun 	u32 ssr[16];	/* 0x200 ~ 0x23c: Security Slave Register */
28*4882a593Smuzhiyun 	u32 sassr[16];	/* 0x240 ~ 0x27c: Security Areas Split Slave Register */
29*4882a593Smuzhiyun 	u32 srtsr[16];	/* 0x280 ~ 0x2bc: Security Region Top Slave */
30*4882a593Smuzhiyun 	u32 spselr[3];	/* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* Bit field in WPMR */
34*4882a593Smuzhiyun #define ATMEL_MATRIX_WPMR_WPKEY	0x4D415400
35*4882a593Smuzhiyun #define ATMEL_MATRIX_WPMR_WPEN	0x00000001
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #endif
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