1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010-2013 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _TEGRA124_GP_PADCTRL_H_ 9*4882a593Smuzhiyun #define _TEGRA124_GP_PADCTRL_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <asm/arch-tegra/gp_padctrl.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* APB_MISC_GP and padctrl registers */ 14*4882a593Smuzhiyun struct apb_misc_gp_ctlr { 15*4882a593Smuzhiyun u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 16*4882a593Smuzhiyun u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 17*4882a593Smuzhiyun u32 reserved0[22]; /* 0x08 - 0x5C: */ 18*4882a593Smuzhiyun u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 19*4882a593Smuzhiyun u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 20*4882a593Smuzhiyun u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 21*4882a593Smuzhiyun u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ 22*4882a593Smuzhiyun u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 23*4882a593Smuzhiyun u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 24*4882a593Smuzhiyun u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ 25*4882a593Smuzhiyun u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ 26*4882a593Smuzhiyun u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ 27*4882a593Smuzhiyun u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ 28*4882a593Smuzhiyun u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ 29*4882a593Smuzhiyun u32 reserved1; /* 0x8C: */ 30*4882a593Smuzhiyun u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ 31*4882a593Smuzhiyun u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ 32*4882a593Smuzhiyun u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ 33*4882a593Smuzhiyun u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ 34*4882a593Smuzhiyun u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ 35*4882a593Smuzhiyun u32 reserved2[3]; /* 0xA4 - 0xAC: */ 36*4882a593Smuzhiyun u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ 37*4882a593Smuzhiyun u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ 38*4882a593Smuzhiyun u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ 39*4882a593Smuzhiyun u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ 40*4882a593Smuzhiyun u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ 41*4882a593Smuzhiyun u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ 42*4882a593Smuzhiyun u32 reserved3[9]; /* 0xC8-0xE8: */ 43*4882a593Smuzhiyun u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ 44*4882a593Smuzhiyun u32 reserved4[3]; /* 0xF0-0xF8: */ 45*4882a593Smuzhiyun u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ 46*4882a593Smuzhiyun u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ 47*4882a593Smuzhiyun u32 reserved5[3]; /* 0x104-0x10C: */ 48*4882a593Smuzhiyun u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ 49*4882a593Smuzhiyun u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ 50*4882a593Smuzhiyun u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ 51*4882a593Smuzhiyun u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ 52*4882a593Smuzhiyun u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ 53*4882a593Smuzhiyun u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ 54*4882a593Smuzhiyun u32 reserved6; /* 0x128: */ 55*4882a593Smuzhiyun u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ 56*4882a593Smuzhiyun u32 reserved7[2]; /* 0x130 - 0x134: */ 57*4882a593Smuzhiyun u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ 58*4882a593Smuzhiyun u32 reserved8[22]; /* 0x13C - 0x190: */ 59*4882a593Smuzhiyun u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ 60*4882a593Smuzhiyun u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ 61*4882a593Smuzhiyun u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ 62*4882a593Smuzhiyun u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ 63*4882a593Smuzhiyun u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ 64*4882a593Smuzhiyun u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ 65*4882a593Smuzhiyun u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* SDMMC1/3 settings from section 27.5 of T114 TRM */ 69*4882a593Smuzhiyun #define SDIOCFG_DRVUP_SLWF 0 70*4882a593Smuzhiyun #define SDIOCFG_DRVDN_SLWR 0 71*4882a593Smuzhiyun #define SDIOCFG_DRVUP 0x24 72*4882a593Smuzhiyun #define SDIOCFG_DRVDN 0x14 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* _TEGRA124_GP_PADCTRL_H_ */ 75