| /OK3568_Linux_fs/kernel/drivers/clk/pistachio/ |
| H A D | clk-pistachio.c | 19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
[all …]
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| /OK3568_Linux_fs/kernel/drivers/memory/tegra/ |
| H A D | tegra20.c | 12 .id = 0x00,
15 .id = 0x01,
18 .id = 0x02,
21 .id = 0x03,
24 .id = 0x04,
27 .id = 0x05,
30 .id = 0x06,
33 .id = 0x07,
36 .id = 0x08,
39 .id = 0x09,
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/marvell/mwifiex/ |
| H A D | cfp.c | 40 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 };
42 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
43 0xb0, 0x48, 0x60, 0x6c, 0 };
45 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96,
46 0x0c, 0x12, 0x18, 0x24,
47 0x30, 0x48, 0x60, 0x6c, 0 };
49 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
50 0xb0, 0x48, 0x60, 0x6c, 0 };
51 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24,
52 0xb0, 0x48, 0x60, 0x6c, 0 };
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/axs10x/ |
| H A D | i2s_pll_clock.c | 22 #define PLL_IDIV_REG 0x0
23 #define PLL_FBDIV_REG 0x4
24 #define PLL_ODIV0_REG 0x8
25 #define PLL_ODIV1_REG 0xC
37 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
38 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
39 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
40 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
41 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
42 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
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| /OK3568_Linux_fs/kernel/drivers/clk/imx/ |
| H A D | clk-imx8mp.c | 424 anatop_base = of_iomap(np, 0); in imx8mp_clocks_probe()
430 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
445 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
453 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe()
454 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe()
455 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe()
456 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe()
457 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe()
458 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe()
459 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe()
[all …]
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| H A D | clk-imx8mn.c | 302 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
311 base = of_iomap(np, 0); in imx8mn_clocks_probe()
318 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
319 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
320 …hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
321 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
322 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
323 …hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
324 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
325 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
|
| H A D | clk-imx8mm.c | 309 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
318 base = of_iomap(np, 0); in imx8mm_clocks_probe()
323 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
324 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
325 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
326 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
327 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
328 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
329 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
330 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
|
| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/ |
| H A D | allwinner,sun8i-a83t-emac.yaml | 74 default: 0
75 minimum: 0
82 default: 0
83 minimum: 0
99 default: 0
100 minimum: 0
142 const: 0
151 "^ethernet-phy@[0-9a-f]$":
177 const: 0
194 reg = <0x01c0b000 0x104>;
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/media/pci/bt8xx/ |
| H A D | bt878.h | 21 #define BT878_VERSION_CODE 0x000000
23 #define BT878_AINT_STAT 0x100
24 #define BT878_ARISCS (0xf<<28)
37 #define BT878_AINT_MASK 0x104
39 #define BT878_AGPIO_DMA_CTL 0x10c
40 #define BT878_A_GAIN (0xf<<28)
47 #define BT878_DA_LRD (0x1f<<16)
52 #define BT878_DA_SDR (0xf<<8)
60 #define BT878_APACK_LEN 0x110
61 #define BT878_AFP_LEN (0xff<<16)
[all …]
|
| /OK3568_Linux_fs/u-boot/board/gdsys/a38x/ |
| H A D | hydra.c | 8 HWVER_100 = 0,
14 { 0x6d5e, 0xcdc1 },
30 uint hardware_version = versions & 0xf; in print_hydra_version()
63 for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) { in hydra_initialize()
89 #define REFL_PATTERN (0xdededede)
94 uint k = 0; in do_hydrate()
96 0x4000); in do_hydrate()
115 res = readl(pcie2_base + 0x118) & 0x1f; in do_hydrate()
118 res = readl(pcie2_base + 0x104); in do_hydrate()
120 printf("Uncorrectable Error Status 0x%08x\n", res); in do_hydrate()
[all …]
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| /OK3568_Linux_fs/kernel/arch/mips/pci/ |
| H A D | pci-vr41xx.h | 12 #define PCIU_BASE 0x0f000c00UL
13 #define PCIU_SIZE 0x200UL
15 #define PCIMMAW1REG 0x00
16 #define PCIMMAW2REG 0x04
17 #define PCITAW1REG 0x08
18 #define PCITAW2REG 0x0c
19 #define PCIMIOAWREG 0x10
20 #define IBA(addr) ((addr) & 0xff000000U)
21 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
22 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723cs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
[all …]
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/arm/display/komeda/d71/ |
| H A D | d71_regs.h | 11 #define BLK_BLOCK_INFO 0x000
12 #define BLK_PIPELINE_INFO 0x004
13 #define BLK_MAX_LINE_SIZE 0x008
14 #define BLK_VALID_INPUT_ID0 0x020
15 #define BLK_OUTPUT_ID0 0x060
16 #define BLK_INPUT_ID0 0x080
17 #define BLK_IRQ_RAW_STATUS 0x0A0
18 #define BLK_IRQ_CLEAR 0x0A4
19 #define BLK_IRQ_MASK 0x0A8
20 #define BLK_IRQ_STATUS 0x0AC
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723ds/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
|
| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/include/ |
| H A D | hal_pg.h | 19 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
20 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
22 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
23 #define PPG_THERMAL_OFFSET_MASK 0x1F
24 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
25 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
26 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
27 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
32 #define EEPROM_ChannelPlan_88E 0xB8
33 #define EEPROM_XTAL_88E 0xB9
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/include/ |
| H A D | hal_pg.h | 20 #define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F
21 #define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0
23 #define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F
24 #define PPG_THERMAL_OFFSET_MASK 0x1F
25 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
26 …TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg…
27 …G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg…
28 #define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01…
33 #define EEPROM_ChannelPlan_88E 0xB8
34 #define EEPROM_XTAL_88E 0xB9
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/ |
| H A D | aidmp.h | 35 #define MFGID_ARM 0x43b
36 #define MFGID_BRCM 0x4bf
37 #define MFGID_MIPS 0x4a7
40 #define CC_SIM 0
43 #define CC_VERIF 0xb
44 #define CC_OPTIMO 0xd
45 #define CC_GEN 0xe
46 #define CC_PRIMECELL 0xf
49 #define ER_EROMENTRY 0x000
50 #define ER_REMAPCONTROL 0xe00
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