1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2018-2019 NXP.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <dt-bindings/clock/imx8mn-clock.h>
7*4882a593Smuzhiyun #include <linux/clk-provider.h>
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "clk.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static u32 share_count_sai2;
19*4882a593Smuzhiyun static u32 share_count_sai3;
20*4882a593Smuzhiyun static u32 share_count_sai5;
21*4882a593Smuzhiyun static u32 share_count_sai6;
22*4882a593Smuzhiyun static u32 share_count_sai7;
23*4882a593Smuzhiyun static u32 share_count_disp;
24*4882a593Smuzhiyun static u32 share_count_pdm;
25*4882a593Smuzhiyun static u32 share_count_nand;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
28*4882a593Smuzhiyun static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
29*4882a593Smuzhiyun static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
30*4882a593Smuzhiyun static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
31*4882a593Smuzhiyun static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
32*4882a593Smuzhiyun static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
33*4882a593Smuzhiyun static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
34*4882a593Smuzhiyun static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
35*4882a593Smuzhiyun static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
38*4882a593Smuzhiyun "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
39*4882a593Smuzhiyun "audio_pll1_out", "sys_pll3_out", };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
44*4882a593Smuzhiyun "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
45*4882a593Smuzhiyun "video_pll1_out", "audio_pll2_out", };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
48*4882a593Smuzhiyun "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
49*4882a593Smuzhiyun "video_pll1_out", "audio_pll2_out", };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
52*4882a593Smuzhiyun "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
53*4882a593Smuzhiyun "video_pll1_out", "sys_pll1_100m",};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
56*4882a593Smuzhiyun "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
57*4882a593Smuzhiyun "video_pll1_out", "sys_pll3_out", };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
60*4882a593Smuzhiyun "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
61*4882a593Smuzhiyun "sys_pll2_250m", "audio_pll1_out", };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m",
64*4882a593Smuzhiyun "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
65*4882a593Smuzhiyun "clk_ext1", "clk_ext4", };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m",
68*4882a593Smuzhiyun "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out",
69*4882a593Smuzhiyun "clk_ext1", "clk_ext3", };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
72*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
73*4882a593Smuzhiyun "clk_ext4", "audio_pll2_out", };
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
76*4882a593Smuzhiyun "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
77*4882a593Smuzhiyun "video_pll1_out", "audio_pll2_out", };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
80*4882a593Smuzhiyun "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
81*4882a593Smuzhiyun "video_pll1_out", "audio_pll2_out", };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
84*4882a593Smuzhiyun "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
85*4882a593Smuzhiyun "video_pll1_out", "audio_pll2_out", };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
88*4882a593Smuzhiyun "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
89*4882a593Smuzhiyun "audio_pll1_out", "video_pll1_out", };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
92*4882a593Smuzhiyun "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
93*4882a593Smuzhiyun "audio_pll1_out", "video_pll1_out", };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
96*4882a593Smuzhiyun "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
97*4882a593Smuzhiyun "audio_pll1_out", "sys_pll1_266m", };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
100*4882a593Smuzhiyun "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
101*4882a593Smuzhiyun "sys_pll2_250m", "audio_pll2_out", };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
104*4882a593Smuzhiyun "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
105*4882a593Smuzhiyun "sys_pll3_out", "clk_ext4", };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
108*4882a593Smuzhiyun "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
109*4882a593Smuzhiyun "clk_ext3", "clk_ext4", };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
112*4882a593Smuzhiyun "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
113*4882a593Smuzhiyun "clk_ext3", "clk_ext4", };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
116*4882a593Smuzhiyun "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
117*4882a593Smuzhiyun "clk_ext2", "clk_ext3", };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
120*4882a593Smuzhiyun "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
121*4882a593Smuzhiyun "clk_ext3", "clk_ext4", };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
124*4882a593Smuzhiyun "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
125*4882a593Smuzhiyun "clk_ext3", "clk_ext4", };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
128*4882a593Smuzhiyun "video_pll1_out", "sys_pll1_133m", "osc_hdmi",
129*4882a593Smuzhiyun "clk_ext2", "clk_ext3", };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
132*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
133*4882a593Smuzhiyun "video_pll1_out", "clk_ext4", };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
136*4882a593Smuzhiyun "clk_ext1", "clk_ext2", "clk_ext3",
137*4882a593Smuzhiyun "clk_ext4", "video_pll1_out", };
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
140*4882a593Smuzhiyun "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
141*4882a593Smuzhiyun "audio_pll2_out", };
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
144*4882a593Smuzhiyun "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
145*4882a593Smuzhiyun "sys_pll2_250m", "video_pll1_out", };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
148*4882a593Smuzhiyun "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
149*4882a593Smuzhiyun "sys_pll3_out", "sys_pll1_100m", };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
152*4882a593Smuzhiyun "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
153*4882a593Smuzhiyun "audio_pll2_out", "sys_pll1_100m", };
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
156*4882a593Smuzhiyun "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
157*4882a593Smuzhiyun "audio_pll2_out", "sys_pll1_100m", };
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
160*4882a593Smuzhiyun "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
161*4882a593Smuzhiyun "audio_pll2_out", "sys_pll1_133m", };
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
164*4882a593Smuzhiyun "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
165*4882a593Smuzhiyun "audio_pll2_out", "sys_pll1_133m", };
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
168*4882a593Smuzhiyun "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
169*4882a593Smuzhiyun "audio_pll2_out", "sys_pll1_133m", };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
172*4882a593Smuzhiyun "sys_pll3_out", "audio_pll1_out", "video_pll1_out",
173*4882a593Smuzhiyun "audio_pll2_out", "sys_pll1_133m", };
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
176*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
177*4882a593Smuzhiyun "clk_ext4", "audio_pll2_out", };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
180*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
181*4882a593Smuzhiyun "clk_ext3", "audio_pll2_out", };
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
184*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
185*4882a593Smuzhiyun "clk_ext4", "audio_pll2_out", };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
188*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
189*4882a593Smuzhiyun "clk_ext3", "audio_pll2_out", };
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
192*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
193*4882a593Smuzhiyun "clk_ext3", "audio_pll2_out", };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m",
196*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
197*4882a593Smuzhiyun "clk_ext3", "audio_pll2_out", };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun static const char * const imx8mn_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
200*4882a593Smuzhiyun "sys_pll2_100m", "sys_pll1_800m", "clk_ext2",
201*4882a593Smuzhiyun "clk_ext4", "audio_pll2_out" };
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
204*4882a593Smuzhiyun "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
205*4882a593Smuzhiyun "sys_pll2_250m", "audio_pll2_out", };
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
208*4882a593Smuzhiyun "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
209*4882a593Smuzhiyun "sys_pll2_250m", "audio_pll2_out", };
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
212*4882a593Smuzhiyun "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
213*4882a593Smuzhiyun "sys_pll1_80m", "video_pll1_out", };
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
216*4882a593Smuzhiyun "sys_pll1_40m", "sys_pll3_out", "clk_ext1",
217*4882a593Smuzhiyun "sys_pll1_80m", "video_pll1_out", };
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
220*4882a593Smuzhiyun "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
221*4882a593Smuzhiyun "sys_pll1_80m", "video_pll1_out", };
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
224*4882a593Smuzhiyun "sys_pll1_40m", "sys_pll3_out", "clk_ext2",
225*4882a593Smuzhiyun "sys_pll1_80m", "video_pll1_out", };
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
228*4882a593Smuzhiyun "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
229*4882a593Smuzhiyun "sys_pll1_80m", "sys_pll2_166m", };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
232*4882a593Smuzhiyun "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
233*4882a593Smuzhiyun "sys_pll2_500m", "sys_pll1_100m", };
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
236*4882a593Smuzhiyun "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
237*4882a593Smuzhiyun "audio_pll2_out", "video_pll1_out", };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
240*4882a593Smuzhiyun "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
241*4882a593Smuzhiyun "audio_pll2_out", "video_pll1_out", };
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
244*4882a593Smuzhiyun "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
245*4882a593Smuzhiyun "audio_pll2_out", "video_pll1_out", };
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
248*4882a593Smuzhiyun "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
249*4882a593Smuzhiyun "audio_pll2_out", "sys_pll1_100m", };
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
252*4882a593Smuzhiyun "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
253*4882a593Smuzhiyun "audio_pll2_out", "video_pll1_out", };
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
256*4882a593Smuzhiyun "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
257*4882a593Smuzhiyun "audio_pll2_out", "video_pll1_out", };
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
260*4882a593Smuzhiyun "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
261*4882a593Smuzhiyun "audio_pll2_out", "video_pll1_out", };
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
264*4882a593Smuzhiyun "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
265*4882a593Smuzhiyun "clk_ext3", "audio_pll2_out", };
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m",
268*4882a593Smuzhiyun "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
269*4882a593Smuzhiyun "sys_pll2_250m", "audio_pll2_out", };
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
272*4882a593Smuzhiyun "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
273*4882a593Smuzhiyun "clk_ext3", "audio_pll2_out", };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy",
278*4882a593Smuzhiyun "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m",
279*4882a593Smuzhiyun "dummy", "sys_pll1_80m", };
280*4882a593Smuzhiyun static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
281*4882a593Smuzhiyun "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
282*4882a593Smuzhiyun "video_pll1_out", "osc_32k", };
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun static struct clk_hw_onecell_data *clk_hw_data;
285*4882a593Smuzhiyun static struct clk_hw **hws;
286*4882a593Smuzhiyun
imx8mn_clocks_probe(struct platform_device * pdev)287*4882a593Smuzhiyun static int imx8mn_clocks_probe(struct platform_device *pdev)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun struct device *dev = &pdev->dev;
290*4882a593Smuzhiyun struct device_node *np = dev->of_node;
291*4882a593Smuzhiyun void __iomem *base;
292*4882a593Smuzhiyun int ret;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
295*4882a593Smuzhiyun IMX8MN_CLK_END), GFP_KERNEL);
296*4882a593Smuzhiyun if (WARN_ON(!clk_hw_data))
297*4882a593Smuzhiyun return -ENOMEM;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun clk_hw_data->num = IMX8MN_CLK_END;
300*4882a593Smuzhiyun hws = clk_hw_data->hws;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
303*4882a593Smuzhiyun hws[IMX8MN_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
304*4882a593Smuzhiyun hws[IMX8MN_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
305*4882a593Smuzhiyun hws[IMX8MN_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
306*4882a593Smuzhiyun hws[IMX8MN_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
307*4882a593Smuzhiyun hws[IMX8MN_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
308*4882a593Smuzhiyun hws[IMX8MN_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
311*4882a593Smuzhiyun base = of_iomap(np, 0);
312*4882a593Smuzhiyun of_node_put(np);
313*4882a593Smuzhiyun if (WARN_ON(!base)) {
314*4882a593Smuzhiyun ret = -ENOMEM;
315*4882a593Smuzhiyun goto unregister_hws;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
319*4882a593Smuzhiyun hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
320*4882a593Smuzhiyun hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
321*4882a593Smuzhiyun hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
322*4882a593Smuzhiyun hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
323*4882a593Smuzhiyun hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
324*4882a593Smuzhiyun hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
325*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
328*4882a593Smuzhiyun hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
329*4882a593Smuzhiyun hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
330*4882a593Smuzhiyun hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
331*4882a593Smuzhiyun hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
332*4882a593Smuzhiyun hws[IMX8MN_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
333*4882a593Smuzhiyun hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
334*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
335*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
336*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /* PLL bypass out */
339*4882a593Smuzhiyun hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
340*4882a593Smuzhiyun hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
341*4882a593Smuzhiyun hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
342*4882a593Smuzhiyun hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
343*4882a593Smuzhiyun hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
344*4882a593Smuzhiyun hws[IMX8MN_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
345*4882a593Smuzhiyun hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
346*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /* PLL out gate */
349*4882a593Smuzhiyun hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
350*4882a593Smuzhiyun hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
351*4882a593Smuzhiyun hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
352*4882a593Smuzhiyun hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
353*4882a593Smuzhiyun hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
354*4882a593Smuzhiyun hws[IMX8MN_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
355*4882a593Smuzhiyun hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
356*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /* SYS PLL1 fixed output */
359*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_40M_CG] = imx_clk_hw_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27);
360*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_80M_CG] = imx_clk_hw_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25);
361*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_100M_CG] = imx_clk_hw_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23);
362*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_133M_CG] = imx_clk_hw_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21);
363*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_160M_CG] = imx_clk_hw_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19);
364*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_200M_CG] = imx_clk_hw_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17);
365*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_266M_CG] = imx_clk_hw_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15);
366*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_400M_CG] = imx_clk_hw_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13);
367*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
370*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
371*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
372*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
373*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
374*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
375*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
376*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
377*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun /* SYS PLL2 fixed output */
380*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_50M_CG] = imx_clk_hw_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27);
381*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_100M_CG] = imx_clk_hw_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25);
382*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_125M_CG] = imx_clk_hw_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23);
383*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_166M_CG] = imx_clk_hw_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21);
384*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_200M_CG] = imx_clk_hw_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19);
385*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_250M_CG] = imx_clk_hw_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17);
386*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_333M_CG] = imx_clk_hw_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15);
387*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_500M_CG] = imx_clk_hw_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13);
388*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
391*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
392*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
393*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
394*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
395*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
396*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
397*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
398*4882a593Smuzhiyun hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun np = dev->of_node;
401*4882a593Smuzhiyun base = devm_platform_ioremap_resource(pdev, 0);
402*4882a593Smuzhiyun if (WARN_ON(IS_ERR(base))) {
403*4882a593Smuzhiyun ret = PTR_ERR(base);
404*4882a593Smuzhiyun goto unregister_hws;
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /* CORE */
408*4882a593Smuzhiyun hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mn_a53_sels, base + 0x8000);
409*4882a593Smuzhiyun hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV];
410*4882a593Smuzhiyun hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV];
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core", imx8mn_gpu_core_sels, base + 0x8180);
413*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader", imx8mn_gpu_shader_sels, base + 0x8200);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE];
416*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE];
417*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE];
418*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER];
419*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER];
420*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER];
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun /* CORE SEL */
423*4882a593Smuzhiyun hws[IMX8MN_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mn_a53_core_sels, ARRAY_SIZE(imx8mn_a53_core_sels));
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun /* BUS */
426*4882a593Smuzhiyun hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800);
427*4882a593Smuzhiyun hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi", imx8mn_enet_axi_sels, base + 0x8880);
428*4882a593Smuzhiyun hws[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900);
429*4882a593Smuzhiyun hws[IMX8MN_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00);
430*4882a593Smuzhiyun hws[IMX8MN_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80);
431*4882a593Smuzhiyun hws[IMX8MN_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80);
432*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00);
433*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80);
434*4882a593Smuzhiyun hws[IMX8MN_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc", imx8mn_noc_sels, base + 0x8d00);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun hws[IMX8MN_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb", imx8mn_ahb_sels, base + 0x9000);
437*4882a593Smuzhiyun hws[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100);
438*4882a593Smuzhiyun hws[IMX8MN_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb", base + 0x9080, 0, 1);
439*4882a593Smuzhiyun hws[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1);
440*4882a593Smuzhiyun hws[IMX8MN_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun /*
443*4882a593Smuzhiyun * DRAM clocks are manipulated from TF-A outside clock framework.
444*4882a593Smuzhiyun * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE
445*4882a593Smuzhiyun * as div value should always be read from hardware
446*4882a593Smuzhiyun */
447*4882a593Smuzhiyun hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
448*4882a593Smuzhiyun hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
451*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
452*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mn_sai3_sels, base + 0xa680);
453*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mn_sai5_sels, base + 0xa780);
454*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI6] = imx8m_clk_hw_composite("sai6", imx8mn_sai6_sels, base + 0xa800);
455*4882a593Smuzhiyun hws[IMX8MN_CLK_SPDIF1] = imx8m_clk_hw_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880);
456*4882a593Smuzhiyun hws[IMX8MN_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980);
457*4882a593Smuzhiyun hws[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00);
458*4882a593Smuzhiyun hws[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80);
459*4882a593Smuzhiyun hws[IMX8MN_CLK_NAND] = imx8m_clk_hw_composite("nand", imx8mn_nand_sels, base + 0xab00);
460*4882a593Smuzhiyun hws[IMX8MN_CLK_QSPI] = imx8m_clk_hw_composite("qspi", imx8mn_qspi_sels, base + 0xab80);
461*4882a593Smuzhiyun hws[IMX8MN_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00);
462*4882a593Smuzhiyun hws[IMX8MN_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80);
463*4882a593Smuzhiyun hws[IMX8MN_CLK_I2C1] = imx8m_clk_hw_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00);
464*4882a593Smuzhiyun hws[IMX8MN_CLK_I2C2] = imx8m_clk_hw_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80);
465*4882a593Smuzhiyun hws[IMX8MN_CLK_I2C3] = imx8m_clk_hw_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00);
466*4882a593Smuzhiyun hws[IMX8MN_CLK_I2C4] = imx8m_clk_hw_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80);
467*4882a593Smuzhiyun hws[IMX8MN_CLK_UART1] = imx8m_clk_hw_composite("uart1", imx8mn_uart1_sels, base + 0xaf00);
468*4882a593Smuzhiyun hws[IMX8MN_CLK_UART2] = imx8m_clk_hw_composite("uart2", imx8mn_uart2_sels, base + 0xaf80);
469*4882a593Smuzhiyun hws[IMX8MN_CLK_UART3] = imx8m_clk_hw_composite("uart3", imx8mn_uart3_sels, base + 0xb000);
470*4882a593Smuzhiyun hws[IMX8MN_CLK_UART4] = imx8m_clk_hw_composite("uart4", imx8mn_uart4_sels, base + 0xb080);
471*4882a593Smuzhiyun hws[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100);
472*4882a593Smuzhiyun hws[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180);
473*4882a593Smuzhiyun hws[IMX8MN_CLK_GIC] = imx8m_clk_hw_composite_critical("gic", imx8mn_gic_sels, base + 0xb200);
474*4882a593Smuzhiyun hws[IMX8MN_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280);
475*4882a593Smuzhiyun hws[IMX8MN_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300);
476*4882a593Smuzhiyun hws[IMX8MN_CLK_PWM1] = imx8m_clk_hw_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380);
477*4882a593Smuzhiyun hws[IMX8MN_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
478*4882a593Smuzhiyun hws[IMX8MN_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
479*4882a593Smuzhiyun hws[IMX8MN_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
480*4882a593Smuzhiyun hws[IMX8MN_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
481*4882a593Smuzhiyun hws[IMX8MN_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
482*4882a593Smuzhiyun hws[IMX8MN_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
483*4882a593Smuzhiyun hws[IMX8MN_CLK_CLKO2] = imx8m_clk_hw_composite("clko2", imx8mn_clko2_sels, base + 0xba80);
484*4882a593Smuzhiyun hws[IMX8MN_CLK_DSI_CORE] = imx8m_clk_hw_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00);
485*4882a593Smuzhiyun hws[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_hw_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80);
486*4882a593Smuzhiyun hws[IMX8MN_CLK_DSI_DBI] = imx8m_clk_hw_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00);
487*4882a593Smuzhiyun hws[IMX8MN_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80);
488*4882a593Smuzhiyun hws[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_hw_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00);
489*4882a593Smuzhiyun hws[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_hw_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80);
490*4882a593Smuzhiyun hws[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_hw_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00);
491*4882a593Smuzhiyun hws[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_hw_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80);
492*4882a593Smuzhiyun hws[IMX8MN_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180);
493*4882a593Smuzhiyun hws[IMX8MN_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mn_pdm_sels, base + 0xc200);
494*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI7] = imx8m_clk_hw_composite("sai7", imx8mn_sai7_sels, base + 0xc300);
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun hws[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0);
497*4882a593Smuzhiyun hws[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0);
498*4882a593Smuzhiyun hws[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0);
499*4882a593Smuzhiyun hws[IMX8MN_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0);
500*4882a593Smuzhiyun hws[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0);
501*4882a593Smuzhiyun hws[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0);
502*4882a593Smuzhiyun hws[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
503*4882a593Smuzhiyun hws[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
504*4882a593Smuzhiyun hws[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
505*4882a593Smuzhiyun hws[IMX8MN_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
506*4882a593Smuzhiyun hws[IMX8MN_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
507*4882a593Smuzhiyun hws[IMX8MN_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
508*4882a593Smuzhiyun hws[IMX8MN_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0);
509*4882a593Smuzhiyun hws[IMX8MN_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0);
510*4882a593Smuzhiyun hws[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0);
511*4882a593Smuzhiyun hws[IMX8MN_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0);
512*4882a593Smuzhiyun hws[IMX8MN_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0);
513*4882a593Smuzhiyun hws[IMX8MN_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0);
514*4882a593Smuzhiyun hws[IMX8MN_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0);
515*4882a593Smuzhiyun hws[IMX8MN_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0);
516*4882a593Smuzhiyun hws[IMX8MN_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand);
517*4882a593Smuzhiyun hws[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand);
518*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2);
519*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2);
520*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3);
521*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI3_IPG] = imx_clk_hw_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3);
522*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5);
523*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
524*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
525*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
526*4882a593Smuzhiyun hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
527*4882a593Smuzhiyun hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
528*4882a593Smuzhiyun hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
529*4882a593Smuzhiyun hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
530*4882a593Smuzhiyun hws[IMX8MN_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0);
531*4882a593Smuzhiyun hws[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0);
532*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_hw_gate4("gpu_core_root_clk", "gpu_core", base + 0x44f0, 0);
533*4882a593Smuzhiyun hws[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0);
534*4882a593Smuzhiyun hws[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0);
535*4882a593Smuzhiyun hws[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0);
536*4882a593Smuzhiyun hws[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0);
537*4882a593Smuzhiyun hws[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0);
538*4882a593Smuzhiyun hws[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0);
539*4882a593Smuzhiyun hws[IMX8MN_CLK_ASRC_ROOT] = imx_clk_hw_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0);
540*4882a593Smuzhiyun hws[IMX8MN_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm);
541*4882a593Smuzhiyun hws[IMX8MN_CLK_PDM_IPG] = imx_clk_hw_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm);
542*4882a593Smuzhiyun hws[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_hw_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp);
543*4882a593Smuzhiyun hws[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_hw_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp);
544*4882a593Smuzhiyun hws[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_hw_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp);
545*4882a593Smuzhiyun hws[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_hw_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp);
546*4882a593Smuzhiyun hws[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0);
547*4882a593Smuzhiyun hws[IMX8MN_CLK_TMU_ROOT] = imx_clk_hw_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0);
548*4882a593Smuzhiyun hws[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0);
549*4882a593Smuzhiyun hws[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0);
550*4882a593Smuzhiyun hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
551*4882a593Smuzhiyun hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
556*4882a593Smuzhiyun hws[IMX8MN_CLK_A53_CORE]->clk,
557*4882a593Smuzhiyun hws[IMX8MN_CLK_A53_CORE]->clk,
558*4882a593Smuzhiyun hws[IMX8MN_ARM_PLL_OUT]->clk,
559*4882a593Smuzhiyun hws[IMX8MN_CLK_A53_DIV]->clk);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun imx_check_clk_hws(hws, IMX8MN_CLK_END);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
564*4882a593Smuzhiyun if (ret < 0) {
565*4882a593Smuzhiyun dev_err(dev, "failed to register hws for i.MX8MN\n");
566*4882a593Smuzhiyun goto unregister_hws;
567*4882a593Smuzhiyun }
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun imx_register_uart_clocks(4);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun return 0;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun unregister_hws:
574*4882a593Smuzhiyun imx_unregister_hw_clocks(hws, IMX8MN_CLK_END);
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun return ret;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun static const struct of_device_id imx8mn_clk_of_match[] = {
580*4882a593Smuzhiyun { .compatible = "fsl,imx8mn-ccm" },
581*4882a593Smuzhiyun { /* Sentinel */ },
582*4882a593Smuzhiyun };
583*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match);
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun static struct platform_driver imx8mn_clk_driver = {
586*4882a593Smuzhiyun .probe = imx8mn_clocks_probe,
587*4882a593Smuzhiyun .driver = {
588*4882a593Smuzhiyun .name = "imx8mn-ccm",
589*4882a593Smuzhiyun /*
590*4882a593Smuzhiyun * Disable bind attributes: clocks are not removed and
591*4882a593Smuzhiyun * reloading the driver will crash or break devices.
592*4882a593Smuzhiyun */
593*4882a593Smuzhiyun .suppress_bind_attrs = true,
594*4882a593Smuzhiyun .of_match_table = of_match_ptr(imx8mn_clk_of_match),
595*4882a593Smuzhiyun },
596*4882a593Smuzhiyun };
597*4882a593Smuzhiyun module_platform_driver(imx8mn_clk_driver);
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
600*4882a593Smuzhiyun MODULE_DESCRIPTION("NXP i.MX8MN clock driver");
601*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
602