1*4882a593Smuzhiyun #include <common.h>
2*4882a593Smuzhiyun #include <console.h> /* ctrlc */
3*4882a593Smuzhiyun #include <asm/io.h>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include "hydra.h"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun enum {
8*4882a593Smuzhiyun HWVER_100 = 0,
9*4882a593Smuzhiyun HWVER_110 = 1,
10*4882a593Smuzhiyun HWVER_120 = 2,
11*4882a593Smuzhiyun };
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static struct pci_device_id hydra_supported[] = {
14*4882a593Smuzhiyun { 0x6d5e, 0xcdc1 },
15*4882a593Smuzhiyun {}
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static struct ihs_fpga *fpga;
19*4882a593Smuzhiyun
get_fpga(void)20*4882a593Smuzhiyun struct ihs_fpga *get_fpga(void)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun return fpga;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
print_hydra_version(uint index)25*4882a593Smuzhiyun void print_hydra_version(uint index)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun u32 versions = readl(&fpga->versions);
28*4882a593Smuzhiyun u32 fpga_version = readl(&fpga->fpga_version);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun uint hardware_version = versions & 0xf;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun printf("FPGA%u: mapped to %p\n ", index, fpga);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun switch (hardware_version) {
35*4882a593Smuzhiyun case HWVER_100:
36*4882a593Smuzhiyun printf("HW-Ver 1.00\n");
37*4882a593Smuzhiyun break;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun case HWVER_110:
40*4882a593Smuzhiyun printf("HW-Ver 1.10\n");
41*4882a593Smuzhiyun break;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun case HWVER_120:
44*4882a593Smuzhiyun printf("HW-Ver 1.20\n");
45*4882a593Smuzhiyun break;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun default:
48*4882a593Smuzhiyun printf("HW-Ver %d(not supported)\n",
49*4882a593Smuzhiyun hardware_version);
50*4882a593Smuzhiyun break;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun printf(" FPGA V %d.%02d\n",
54*4882a593Smuzhiyun fpga_version / 100, fpga_version % 100);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
hydra_initialize(void)57*4882a593Smuzhiyun void hydra_initialize(void)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun uint i;
60*4882a593Smuzhiyun pci_dev_t devno;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Find and probe all the matching PCI devices */
63*4882a593Smuzhiyun for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
64*4882a593Smuzhiyun u32 val;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Try to enable I/O accesses and bus-mastering */
67*4882a593Smuzhiyun val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
68*4882a593Smuzhiyun pci_write_config_dword(devno, PCI_COMMAND, val);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Make sure it worked */
71*4882a593Smuzhiyun pci_read_config_dword(devno, PCI_COMMAND, &val);
72*4882a593Smuzhiyun if (!(val & PCI_COMMAND_MEMORY)) {
73*4882a593Smuzhiyun puts("Can't enable I/O memory\n");
74*4882a593Smuzhiyun continue;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun if (!(val & PCI_COMMAND_MASTER)) {
77*4882a593Smuzhiyun puts("Can't enable bus-mastering\n");
78*4882a593Smuzhiyun continue;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* read FPGA details */
82*4882a593Smuzhiyun fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
83*4882a593Smuzhiyun PCI_REGION_MEM);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun print_hydra_version(i);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define REFL_PATTERN (0xdededede)
90*4882a593Smuzhiyun #define REFL_PATTERN_INV (~REFL_PATTERN)
91*4882a593Smuzhiyun
do_hydrate(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])92*4882a593Smuzhiyun int do_hydrate(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun uint k = 0;
95*4882a593Smuzhiyun void __iomem *pcie2_base = (void __iomem *)(MVEBU_REG_PCIE_BASE +
96*4882a593Smuzhiyun 0x4000);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (!fpga)
99*4882a593Smuzhiyun return -1;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun while (1) {
102*4882a593Smuzhiyun u32 res;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun writel(REFL_PATTERN, &fpga->reflection_low);
105*4882a593Smuzhiyun res = readl(&fpga->reflection_low);
106*4882a593Smuzhiyun if (res != REFL_PATTERN_INV)
107*4882a593Smuzhiyun printf("round %u: read %08x, expected %08x\n",
108*4882a593Smuzhiyun k, res, REFL_PATTERN_INV);
109*4882a593Smuzhiyun writel(REFL_PATTERN_INV, &fpga->reflection_low);
110*4882a593Smuzhiyun res = readl(&fpga->reflection_low);
111*4882a593Smuzhiyun if (res != REFL_PATTERN)
112*4882a593Smuzhiyun printf("round %u: read %08x, expected %08x\n",
113*4882a593Smuzhiyun k, res, REFL_PATTERN);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun res = readl(pcie2_base + 0x118) & 0x1f;
116*4882a593Smuzhiyun if (res)
117*4882a593Smuzhiyun printf("FrstErrPtr %u\n", res);
118*4882a593Smuzhiyun res = readl(pcie2_base + 0x104);
119*4882a593Smuzhiyun if (res) {
120*4882a593Smuzhiyun printf("Uncorrectable Error Status 0x%08x\n", res);
121*4882a593Smuzhiyun writel(res, pcie2_base + 0x104);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (!(++k % 10000))
125*4882a593Smuzhiyun printf("round %u\n", k);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (ctrlc())
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun U_BOOT_CMD(
135*4882a593Smuzhiyun hydrate, 1, 0, do_hydrate,
136*4882a593Smuzhiyun "hydra reflection test",
137*4882a593Smuzhiyun "hydra reflection test"
138*4882a593Smuzhiyun );
139