1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun bt878.h - Bt878 audio module (register offsets) 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _BT878_H_ 10*4882a593Smuzhiyun #define _BT878_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/interrupt.h> 13*4882a593Smuzhiyun #include <linux/pci.h> 14*4882a593Smuzhiyun #include <linux/sched.h> 15*4882a593Smuzhiyun #include <linux/spinlock.h> 16*4882a593Smuzhiyun #include <linux/mutex.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include "bt848.h" 19*4882a593Smuzhiyun #include "bttv.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define BT878_VERSION_CODE 0x000000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define BT878_AINT_STAT 0x100 24*4882a593Smuzhiyun #define BT878_ARISCS (0xf<<28) 25*4882a593Smuzhiyun #define BT878_ARISC_EN (1<<27) 26*4882a593Smuzhiyun #define BT878_ASCERR (1<<19) 27*4882a593Smuzhiyun #define BT878_AOCERR (1<<18) 28*4882a593Smuzhiyun #define BT878_APABORT (1<<17) 29*4882a593Smuzhiyun #define BT878_ARIPERR (1<<16) 30*4882a593Smuzhiyun #define BT878_APPERR (1<<15) 31*4882a593Smuzhiyun #define BT878_AFDSR (1<<14) 32*4882a593Smuzhiyun #define BT878_AFTRGT (1<<13) 33*4882a593Smuzhiyun #define BT878_AFBUS (1<<12) 34*4882a593Smuzhiyun #define BT878_ARISCI (1<<11) 35*4882a593Smuzhiyun #define BT878_AOFLOW (1<<3) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define BT878_AINT_MASK 0x104 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define BT878_AGPIO_DMA_CTL 0x10c 40*4882a593Smuzhiyun #define BT878_A_GAIN (0xf<<28) 41*4882a593Smuzhiyun #define BT878_A_G2X (1<<27) 42*4882a593Smuzhiyun #define BT878_A_PWRDN (1<<26) 43*4882a593Smuzhiyun #define BT878_A_SEL (3<<24) 44*4882a593Smuzhiyun #define BT878_DA_SCE (1<<23) 45*4882a593Smuzhiyun #define BT878_DA_LRI (1<<22) 46*4882a593Smuzhiyun #define BT878_DA_MLB (1<<21) 47*4882a593Smuzhiyun #define BT878_DA_LRD (0x1f<<16) 48*4882a593Smuzhiyun #define BT878_DA_DPM (1<<15) 49*4882a593Smuzhiyun #define BT878_DA_SBR (1<<14) 50*4882a593Smuzhiyun #define BT878_DA_ES2 (1<<13) 51*4882a593Smuzhiyun #define BT878_DA_LMT (1<<12) 52*4882a593Smuzhiyun #define BT878_DA_SDR (0xf<<8) 53*4882a593Smuzhiyun #define BT878_DA_IOM (3<<6) 54*4882a593Smuzhiyun #define BT878_DA_APP (1<<5) 55*4882a593Smuzhiyun #define BT878_ACAP_EN (1<<4) 56*4882a593Smuzhiyun #define BT878_PKTP (3<<2) 57*4882a593Smuzhiyun #define BT878_RISC_EN (1<<1) 58*4882a593Smuzhiyun #define BT878_FIFO_EN 1 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define BT878_APACK_LEN 0x110 61*4882a593Smuzhiyun #define BT878_AFP_LEN (0xff<<16) 62*4882a593Smuzhiyun #define BT878_ALP_LEN 0xfff 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define BT878_ARISC_START 0x114 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define BT878_ARISC_PC 0x120 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* BT878 FUNCTION 0 REGISTERS */ 69*4882a593Smuzhiyun #define BT878_GPIO_DMA_CTL 0x10c 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Interrupt register */ 72*4882a593Smuzhiyun #define BT878_INT_STAT 0x100 73*4882a593Smuzhiyun #define BT878_INT_MASK 0x104 74*4882a593Smuzhiyun #define BT878_I2CRACK (1<<25) 75*4882a593Smuzhiyun #define BT878_I2CDONE (1<<8) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define BT878_MAX 4 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define BT878_RISC_SYNC_MASK (1 << 15) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define BTTV_BOARD_UNKNOWN 0x00 83*4882a593Smuzhiyun #define BTTV_BOARD_PINNACLESAT 0x5e 84*4882a593Smuzhiyun #define BTTV_BOARD_NEBULA_DIGITV 0x68 85*4882a593Smuzhiyun #define BTTV_BOARD_PC_HDTV 0x70 86*4882a593Smuzhiyun #define BTTV_BOARD_TWINHAN_DST 0x71 87*4882a593Smuzhiyun #define BTTV_BOARD_AVDVBT_771 0x7b 88*4882a593Smuzhiyun #define BTTV_BOARD_AVDVBT_761 0x7c 89*4882a593Smuzhiyun #define BTTV_BOARD_DVICO_DVBT_LITE 0x80 90*4882a593Smuzhiyun #define BTTV_BOARD_DVICO_FUSIONHDTV_5_LITE 0x87 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun extern int bt878_num; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct bt878 { 95*4882a593Smuzhiyun struct mutex gpio_lock; 96*4882a593Smuzhiyun unsigned int nr; 97*4882a593Smuzhiyun unsigned int bttv_nr; 98*4882a593Smuzhiyun struct i2c_adapter *adapter; 99*4882a593Smuzhiyun struct pci_dev *dev; 100*4882a593Smuzhiyun unsigned int id; 101*4882a593Smuzhiyun unsigned int TS_Size; 102*4882a593Smuzhiyun unsigned char revision; 103*4882a593Smuzhiyun unsigned int irq; 104*4882a593Smuzhiyun unsigned long bt878_adr; 105*4882a593Smuzhiyun volatile void __iomem *bt878_mem; /* function 1 */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun volatile u32 finished_block; 108*4882a593Smuzhiyun volatile u32 last_block; 109*4882a593Smuzhiyun u32 block_count; 110*4882a593Smuzhiyun u32 block_bytes; 111*4882a593Smuzhiyun u32 line_bytes; 112*4882a593Smuzhiyun u32 line_count; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun u32 buf_size; 115*4882a593Smuzhiyun u8 *buf_cpu; 116*4882a593Smuzhiyun dma_addr_t buf_dma; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun u32 risc_size; 119*4882a593Smuzhiyun __le32 *risc_cpu; 120*4882a593Smuzhiyun dma_addr_t risc_dma; 121*4882a593Smuzhiyun u32 risc_pos; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct tasklet_struct tasklet; 124*4882a593Smuzhiyun int shutdown; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun extern struct bt878 bt878[BT878_MAX]; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun void bt878_start(struct bt878 *bt, u32 controlreg, u32 op_sync_orin, 130*4882a593Smuzhiyun u32 irq_err_ignore); 131*4882a593Smuzhiyun void bt878_stop(struct bt878 *bt); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define bmtwrite(dat,adr) writel((dat), (adr)) 134*4882a593Smuzhiyun #define bmtread(adr) readl(adr) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif 137