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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc512x_lpbfifo.txt16 reg = <0x10100 0x50>;
17 interrupts = <7 0x8>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mips/cavium/
H A Dciu3.txt24 #address-cells = <0>;
26 reg = <0x10100 0x00000000 0x0 0xb0000000>;
/OK3568_Linux_fs/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dorion5x.h23 #define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500))
24 #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
25 #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
26 #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
27 #define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000))
28 #define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100))
29 #define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000))
30 #define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100))
31 #define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300))
32 #define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000))
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dsoc.h17 #define INTREG_BASE 0xd0000000
19 #define KW_OFFSET_REG (INTREG_BASE + 0x20080)
22 #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
23 #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
25 #define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
26 #define KW_TWSI_BASE (KW_REGISTER(0x11000))
27 #define KW_UART0_BASE (KW_REGISTER(0x12000))
28 #define KW_UART1_BASE (KW_REGISTER(0x12100))
29 #define KW_MPP_BASE (KW_REGISTER(0x10000))
30 #define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
[all …]
/OK3568_Linux_fs/kernel/arch/m68k/include/asm/
H A Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rmobile/include/mach/
H A Dehci-rmobile.h12 #define OHCI_OFFSET 0x00
13 #define OHCI_SIZE 0x1000
14 #define EHCI_OFFSET 0x1000
15 #define EHCI_SIZE 0x1000
17 #define EHCI_USBCMD (EHCI_OFFSET + 0x0020)
23 #define USBH_RST (1 << 0)
32 #define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0))
36 #define AHB_CFG_AHBPCI 0x40000000
37 #define AHB_CFG_HOST 0x80000000
56 #define MMODE_HTRANS (1 << 0)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
H A Didle-states.yaml82 between 0 and infinite time, until a wake-up event occurs.
107 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
147 0| 1 time(ms)
152 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
332 #size-cells = <0>;
335 cpu@0 {
338 reg = <0x0 0x0>;
347 reg = <0x0 0x1>;
356 reg = <0x0 0x100>;
365 reg = <0x0 0x101>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dorion5x.dtsi29 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
30 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
33 clocks = <&core_clk 0>;
39 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
40 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
43 clocks = <&core_clk 0>;
49 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
50 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
53 clocks = <&core_clk 0>;
59 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
[all …]
H A Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
/OK3568_Linux_fs/kernel/drivers/crypto/mediatek/
H A Dmtk-regs.h13 #define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12))
14 #define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12))
15 #define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12))
16 #define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12))
17 #define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12))
18 #define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12))
19 #define CDR_RING_SIZE(x) (0x18 + ((x) << 12))
20 #define CDR_DESC_SIZE(x) (0x1C + ((x) << 12))
21 #define CDR_CFG(x) (0x20 + ((x) << 12))
22 #define CDR_DMA_CFG(x) (0x24 + ((x) << 12))
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dmpc5125twr.dts30 #size-cells = <0>;
32 PowerPC,5125@0 {
34 reg = <0>;
35 d-cache-line-size = <0x20>; // 32 bytes
36 i-cache-line-size = <0x20>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
47 reg = <0x00000000 0x10000000>; // 256MB at 0
52 reg = <0x30000000 0x08000>; // 32K at 0x30000000
57 #size-cells = <0>;
[all …]
H A Dmpc5121.dtsi26 #size-cells = <0>;
28 PowerPC,5121@0 {
30 reg = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
32 i-cache-line-size = <0x20>; /* 32 bytes */
33 d-cache-size = <0x8000>; /* L1, 32K */
34 i-cache-size = <0x8000>; /* L1, 32K */
43 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
48 reg = <0x20000000 0x4000>;
49 interrupts = <66 0x8>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x000>;
54 reg = <0x0 0x100>;
60 reg = <0x0 0x200>;
66 reg = <0x0 0x300>;
72 reg = <0x0 0x10000>;
78 reg = <0x0 0x10100>;
84 reg = <0x0 0x10200>;
[all …]
/OK3568_Linux_fs/kernel/drivers/rapidio/switches/
H A Didt_gen3.c18 #define RIO_EM_PW_STAT 0x40020
19 #define RIO_PW_CTL 0x40204
20 #define RIO_PW_CTL_PW_TMR 0xffffff00
21 #define RIO_PW_ROUTE 0x40208
23 #define RIO_EM_DEV_INT_EN 0x40030
25 #define RIO_PLM_SPx_IMP_SPEC_CTL(x) (0x10100 + (x)*0x100)
26 #define RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST 0x02000000
28 #define RIO_PLM_SPx_PW_EN(x) (0x10118 + (x)*0x100)
29 #define RIO_PLM_SPx_PW_EN_OK2U 0x40000000
30 #define RIO_PLM_SPx_PW_EN_LINIT 0x10000000
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc8xxx/
H A Dsrio.c15 #define SRIO_PORT_ACCEPT_ALL 0x10000001
16 #define SRIO_IB_ATMU_AR 0x80f55000
17 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
18 #define SRIO_OB_ATMU_AR_RW 0x80045000
19 #define SRIO_LCSBA1CSR_OFFSET 0x5c
20 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
21 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
22 #define SRIO_LCSBA1CSR 0x60000000
63 * on lane 0, 4x to 1x on lane R (redundant lane).
84 >> (12 - port * 4)) & 0x3; in srio_erratum_a004034()
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/qla4xxx/
H A Dql4_nx.h13 #define PHAN_INITIALIZE_FAILED 0xffff
14 #define PHAN_INITIALIZE_COMPLETE 0xff01
17 #define PHAN_INITIALIZE_ACK 0xf00f
18 #define PHAN_PEG_RCV_INITIALIZED 0xff01
21 #define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))
23 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
24 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
25 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
26 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
31 #define qla82xx_get_temp_state(x) ((x) & 0xffff)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hdr.h20 QLCNIC_HW_H0_CH_HUB_ADR = 0x05,
21 QLCNIC_HW_H1_CH_HUB_ADR = 0x0E,
22 QLCNIC_HW_H2_CH_HUB_ADR = 0x03,
23 QLCNIC_HW_H3_CH_HUB_ADR = 0x01,
24 QLCNIC_HW_H4_CH_HUB_ADR = 0x06,
25 QLCNIC_HW_H5_CH_HUB_ADR = 0x07,
26 QLCNIC_HW_H6_CH_HUB_ADR = 0x08
29 /* Hub 0 */
31 QLCNIC_HW_MN_CRB_AGT_ADR = 0x15,
32 QLCNIC_HW_MS_CRB_AGT_ADR = 0x25
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/qla2xxx/
H A Dqla_nx.h15 #define PHAN_INITIALIZE_FAILED 0xffff
16 #define PHAN_INITIALIZE_COMPLETE 0xff01
19 #define PHAN_INITIALIZE_ACK 0xf00f
20 #define PHAN_PEG_RCV_INITIALIZED 0xff01
23 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
26 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
27 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
28 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
29 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
30 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.h21 #define MTK_TX_DMA_BUF_LEN 0x3fff
27 #define MTK_DMA_DUMMY_DESC 0xffffffff
61 #define MTK_RST_GL 0x04
62 #define RST_GL_PSE BIT(0)
65 #define MTK_INT_STATUS2 0x08
70 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
73 #define MTK_FE_INT_GRP 0x20
76 #define MTK_CDMQ_IG_CTRL 0x1400
77 #define MTK_CDMQ_STAG_EN BIT(0)
80 #define MTK_CDMP_EG_CTRL 0x404
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/src/mbgl/util/
H A Di18n.cpp19 // The following table comes from <http://www.unicode.org/Public/10.0.0/ucd/Blocks.txt>.
22 // DEFINE_IS_IN_UNICODE_BLOCK(BasicLatin, 0x0000, 0x007F)
23 DEFINE_IS_IN_UNICODE_BLOCK(Latin1Supplement, 0x0080, 0x00FF)
24 // DEFINE_IS_IN_UNICODE_BLOCK(LatinExtendedA, 0x0100, 0x017F)
25 // DEFINE_IS_IN_UNICODE_BLOCK(LatinExtendedB, 0x0180, 0x024F)
26 // DEFINE_IS_IN_UNICODE_BLOCK(IPAExtensions, 0x0250, 0x02AF)
27 // DEFINE_IS_IN_UNICODE_BLOCK(SpacingModifierLetters, 0x02B0, 0x02FF)
28 // DEFINE_IS_IN_UNICODE_BLOCK(CombiningDiacriticalMarks, 0x0300, 0x036F)
29 // DEFINE_IS_IN_UNICODE_BLOCK(GreekandCoptic, 0x0370, 0x03FF)
30 // DEFINE_IS_IN_UNICODE_BLOCK(Cyrillic, 0x0400, 0x04FF)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/ast/
H A Dast_post.c44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); in ast_enable_vga()
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); in ast_enable_vga()
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_enable_mmio()
63 return !!(ch & 0x01); in ast_is_vga_enabled()
66 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
67 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
68 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
78 for (i = 0x81; i <= 0x9f; i++) in ast_set_def_ext_reg()
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
83 if (dev->pdev->revision >= 0x20) in ast_set_def_ext_reg()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_hwimg_raw_data_8852b.h36 0x704, 0x601E0100,
37 0x4000, 0x00000000,
38 0x4004, 0xCA014000,
39 0x4008, 0xC751D4F0,
40 0x400C, 0x44511475,
41 0x4010, 0x00000000,
42 0x4014, 0x00000000,
43 0x4018, 0x4F4C084B,
44 0x401C, 0x084A4E52,
45 0x4020, 0x4D504E4B,
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/
H A Dhalbb_hwimg_raw_data_8852b.h36 0x704, 0x601E0100,
37 0x4000, 0x00000000,
38 0x4004, 0xCA014000,
39 0x4008, 0xC751D4F0,
40 0x400C, 0x44511475,
41 0x4010, 0x00000000,
42 0x4014, 0x00000000,
43 0x4018, 0x4F4C084B,
44 0x401C, 0x084A4E52,
45 0x4020, 0x4D504E4B,
[all …]

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