Lines Matching +full:0 +full:x10100
29 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
30 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
33 clocks = <&core_clk 0>;
39 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
40 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
43 clocks = <&core_clk 0>;
49 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
50 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
53 clocks = <&core_clk 0>;
59 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
60 ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
63 clocks = <&core_clk 0>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
77 reg = <0x10100 0x40>;
87 #size-cells = <0>;
88 cell-index = <0>;
89 reg = <0x10600 0x28>;
95 reg = <0x11000 0x20>;
97 #size-cells = <0>;
99 clocks = <&core_clk 0>;
105 reg = <0x12000 0x100>;
108 clocks = <&core_clk 0>;
114 reg = <0x12100 0x100>;
117 clocks = <&core_clk 0>;
125 reg = <0x20110 0x8>;
126 interrupts = <0>;
134 reg = <0x20200 0x08>;
139 reg = <0x20300 0x20>;
142 clocks = <&core_clk 0>;
147 reg = <0x20300 0x28>, <0x20108 0x4>;
150 clocks = <&core_clk 0>;
156 reg = <0x50000 0x1000>;
163 reg = <0x60900 0x100
164 0x60b00 0x100>;
183 #size-cells = <0>;
184 reg = <0x72000 0x4000>;
188 ethport: ethernet-port@0 {
190 reg = <0>;
201 #size-cells = <0>;
202 reg = <0x72004 0x84>;
211 reg = <0x80000 0x5000>;
218 reg = <0x90000 0x10000>;
222 marvell,crypto-sram-size = <0x800>;
228 reg = <0xa0000 0x1000>;
236 reg = <MBUS_ID(0x09, 0x00) 0x0 0x800>;