1*4882a593Smuzhiyun* Central Interrupt Unit v3 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunProperties: 4*4882a593Smuzhiyun- compatible: "cavium,octeon-7890-ciu3" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Compatibility with 78XX and 73XX SOCs. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- interrupt-controller: This is an interrupt controller. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- reg: The base address of the CIU's register bank. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- #interrupt-cells: Must be <2>. The first cell is source number. 13*4882a593Smuzhiyun The second cell indicates the triggering semantics, and may have a 14*4882a593Smuzhiyun value of either 4 for level semantics, or 1 for edge semantics. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun interrupt-controller@1010000000000 { 18*4882a593Smuzhiyun compatible = "cavium,octeon-7890-ciu3"; 19*4882a593Smuzhiyun interrupt-controller; 20*4882a593Smuzhiyun /* Interrupts are specified by two parts: 21*4882a593Smuzhiyun * 1) Source number (20 significant bits) 22*4882a593Smuzhiyun * 2) Trigger type: (4 == level, 1 == edge) 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #address-cells = <0>; 25*4882a593Smuzhiyun #interrupt-cells = <2>; 26*4882a593Smuzhiyun reg = <0x10100 0x00000000 0x0 0xb0000000>; 27*4882a593Smuzhiyun }; 28